diff options
author | wdenk <wdenk> | 2004-02-22 23:46:08 (GMT) |
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committer | wdenk <wdenk> | 2004-02-22 23:46:08 (GMT) |
commit | 3c74e32a98187c792edcea3e0e39150de5a8dda6 (patch) | |
tree | feb1a080a1332a3bfc383282ba9a6e4cfe6f8f4a /cpu/ppc4xx/405gp_pci.c | |
parent | cf56e1101957c09cb4aafcf28a89658c4649c511 (diff) | |
download | u-boot-3c74e32a98187c792edcea3e0e39150de5a8dda6.tar.xz |
* Patch by Travis Sawyer, 09 Feb 2004:
o 440GX:
- Fix PCI Indirect access for type 1 config cycles with ppc440.
- Add phymode for 440 enet
- fix pci pre init
o XPedite1K:
- Change board_pre_init to board_early_init_f
- Add user flash to bus controller setup
- Fix pci pre init
- Fix is_pci_host to check GPIO for monarch bit
- Force xpedite1k to pci conventional mode (via #define option)
* Patch by Brad Kemp, 4 Feb 2004:
- handle the machine check that is generated during the PCI scans
on 82xx processors.
- define the registers used in the IMMR by the PCI subsystem.
* Patch by Pierre Aubert, 03 Feb 2004:
cpu/mpc5xxx/start.S: copy MBAR into SPR311
* Patch by Jeff Angielski, 03 Feb 2004:
Fix copy & paste error in cpu/mpc8260/pci.c
* Patch by Reinhard Meyer, 24 Jan 2004:
Fix typo in cpu/mpc5xxx/pci_mpc5200.c
Diffstat (limited to 'cpu/ppc4xx/405gp_pci.c')
-rw-r--r-- | cpu/ppc4xx/405gp_pci.c | 33 |
1 files changed, 23 insertions, 10 deletions
diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c index d3f6b23..c9e2e9c 100644 --- a/cpu/ppc4xx/405gp_pci.c +++ b/cpu/ppc4xx/405gp_pci.c @@ -411,15 +411,23 @@ void pci_440_init (struct pci_controller *hose) /*--------------------------------------------------------------------------+ * The PCI initialization sequence enable bit must be set ... if not abort - * pci setup since updating the bit requires chip reset. + * pci setup since updating the bit requires chip reset. *--------------------------------------------------------------------------*/ - strap = mfdcr(cpc0_strp1); - if( (strap & 0x00040000) == 0 ){ - printf("PCI: CPC0_STRP1[PISE] not set.\n"); - printf("PCI: Configuration aborted.\n"); - return; - } - +#if defined (CONFIG_440_GX) + mfsdr(sdr_sdstp1,strap); + if ( (strap & 0x00010000) == 0 ){ + printf("PCI: SDR0_STRP1[PISE] not set.\n"); + printf("PCI: Configuration aborted.\n"); + return; + } +#else + strap = mfdcr(cpc0_strp1); + if( (strap & 0x00040000) == 0 ){ + printf("PCI: CPC0_STRP1[PISE] not set.\n"); + printf("PCI: Configuration aborted.\n"); + return; + } +#endif /*--------------------------------------------------------------------------+ * PCI controller init *--------------------------------------------------------------------------*/ @@ -463,8 +471,13 @@ void pci_440_init (struct pci_controller *hose) out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */ #endif - out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */ - out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */ +#if defined(CONFIG_440_GX) + out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */ + out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */ +#else + out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */ + out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */ +#endif /*--------------------------------------------------------------------------+ * PCI master init: default is one 256MB region for PCI memory: |