diff options
| author | Stefan Roese <sr@denx.de> | 2007-10-22 08:30:38 (GMT) |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-10-31 20:20:50 (GMT) |
| commit | 764e7417ee5f6e25b1715720e7d7dd3487109385 (patch) | |
| tree | 66c6a025327fb80f6816508fb389b0f6b5cecee7 /cpu/ppc4xx/serial.c | |
| parent | 211ea91ac6c225bec7e668a03d0ba7d7310679fa (diff) | |
| download | u-boot-764e7417ee5f6e25b1715720e7d7dd3487109385.tar.xz | |
ppc4xx: Correct UART input clock calculation and passing to fdt
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu/ppc4xx/serial.c')
| -rw-r--r-- | cpu/ppc4xx/serial.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c index 8b1e2ff..0fdef7e 100644 --- a/cpu/ppc4xx/serial.c +++ b/cpu/ppc4xx/serial.c @@ -528,12 +528,18 @@ int serial_init(void) udiv = 1; tmp = gd->baudrate * 16; bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp; + gd->freqUART = CFG_EXT_SERIAL_CLOCK; #else /* For 440, the cpu clock is on divider chain A, UART on divider * chain B ... so cpu clock is irrelevant. Get the "optimized" * values that are subject to the 1/2 opb clock constraint */ serial_divs (gd->baudrate, &udiv, &bdiv); + + /* Correct UART frequency in bd-info struct now that + * the UART divisor is available + */ + gd->freqUART = gd->freqUART / udiv; #endif reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */ @@ -644,6 +650,15 @@ int serial_init (void) bdiv = (clk + tmp / 2) / tmp; #endif /* CONFIG_405EX */ + /* Correct UART frequency in bd-info struct now that + * the UART divisor is available + */ +#ifdef CFG_EXT_SERIAL_CLOCK + gd->freqUART = CFG_EXT_SERIAL_CLOCK; +#else + gd->freqUART = gd->freqUART / udiv; +#endif + out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */ out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */ out8(UART_BASE + UART_DLM, bdiv >> 8); /* set baudrate divisor */ |