diff options
author | Niklaus Giger <niklaus.giger@member.fsf.org> | 2009-10-04 18:04:20 (GMT) |
---|---|---|
committer | Stefan Roese <sr@denx.de> | 2009-10-07 07:15:20 (GMT) |
commit | ddc922ff2c20ae0b7f9ce2df1ac28143e2f325bd (patch) | |
tree | 5c390395480e4cfd575ef751edd34034eaffa142 /cpu/ppc4xx | |
parent | f80e61dcfe53fa3a5936659883415c9bd1b5a3d9 (diff) | |
download | u-boot-ddc922ff2c20ae0b7f9ce2df1ac28143e2f325bd.tar.xz |
ppc_4xx: Apply new HW register names
Modify all existing *.c files to use the new register names
as seen in the AMCC manuals.
Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu/ppc4xx')
-rw-r--r-- | cpu/ppc4xx/4xx_pci.c | 48 | ||||
-rw-r--r-- | cpu/ppc4xx/cpu_init.c | 4 | ||||
-rw-r--r-- | cpu/ppc4xx/miiphy.c | 24 | ||||
-rw-r--r-- | cpu/ppc4xx/speed.c | 6 |
4 files changed, 41 insertions, 41 deletions
diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c index e97f32c..fa521f0 100644 --- a/cpu/ppc4xx/4xx_pci.c +++ b/cpu/ppc4xx/4xx_pci.c @@ -518,7 +518,7 @@ int pci_440_init (struct pci_controller *hose) /* PCI I/O space */ pci_set_region(hose->regions + reg_num++, 0x00000000, - PCIX0_IOBASE, + PCIL0_IOBASE, 0x10000, PCI_REGION_IO); @@ -545,7 +545,7 @@ int pci_440_init (struct pci_controller *hose) hose->region_count = reg_num; - pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA); + pci_setup_indirect(hose, PCIL0_CFGADR, PCIL0_CFGDATA); /* Let board change/modify hose & do initial checks */ if (pci_pre_init (hose) == 0) { @@ -562,18 +562,18 @@ int pci_440_init (struct pci_controller *hose) #if defined(CONFIG_SYS_PCI_TARGET_INIT) pci_target_init(hose); /* Let board setup pci target */ #else - out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID ); - out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */ + out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID ); + out16r( PCIL0_CLS, 0x00060000 ); /* Bridge, host bridge */ #endif #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) - out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */ - out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */ -#elif defined(PCIX0_BRDGOPT1) - out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */ - out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */ + out32r( PCIL0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */ + out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */ +#elif defined(PCIL0_BRDGOPT1) + out32r( PCIL0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */ + out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 1 ); /* Enable host config */ #endif /*--------------------------------------------------------------------------+ @@ -583,23 +583,23 @@ int pci_440_init (struct pci_controller *hose) #if defined(CONFIG_SYS_PCI_MASTER_INIT) pci_master_init(hose); /* Let board setup pci master */ #else - out32r( PCIX0_POM0SA, 0 ); /* disable */ - out32r( PCIX0_POM1SA, 0 ); /* disable */ - out32r( PCIX0_POM2SA, 0 ); /* disable */ + out32r( PCIL0_POM0SA, 0 ); /* disable */ + out32r( PCIL0_POM1SA, 0 ); /* disable */ + out32r( PCIL0_POM2SA, 0 ); /* disable */ #if defined(CONFIG_440SPE) - out32r( PCIX0_POM0LAL, 0x10000000 ); - out32r( PCIX0_POM0LAH, 0x0000000c ); + out32r( PCIL0_POM0LAL, 0x10000000 ); + out32r( PCIL0_POM0LAH, 0x0000000c ); #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) - out32r( PCIX0_POM0LAL, 0x20000000 ); - out32r( PCIX0_POM0LAH, 0x0000000c ); + out32r( PCIL0_POM0LAL, 0x20000000 ); + out32r( PCIL0_POM0LAH, 0x0000000c ); #else - out32r( PCIX0_POM0LAL, 0x00000000 ); - out32r( PCIX0_POM0LAH, 0x00000003 ); + out32r( PCIL0_POM0LAL, 0x00000000 ); + out32r( PCIL0_POM0LAH, 0x00000003 ); #endif - out32r( PCIX0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE ); - out32r( PCIX0_POM0PCIAH, 0x00000000 ); - out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */ - out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 ); + out32r( PCIL0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE ); + out32r( PCIL0_POM0PCIAH, 0x00000000 ); + out32r( PCIL0_POM0SA, 0xf0000001 ); /* 256MB, enabled */ + out32r( PCIL0_STS, in32r( PCIL0_STS ) & ~0x0000fff8 ); #endif /*--------------------------------------------------------------------------+ @@ -614,7 +614,7 @@ int pci_440_init (struct pci_controller *hose) #endif #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \ !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) - out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER); + out16r( PCIL0_CMD, in16r( PCIL0_CMD ) | PCI_COMMAND_MASTER); #endif hose->last_busno = pci_hose_scan(hose); } diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index bd06b9b..a00da40 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -58,13 +58,13 @@ void reconfigure_pll(u32 new_cpu_freq) target_perdv0 = 4; target_spcid0 = 4; - mfcpr(CPR0_PRIMBD, reg); + mfcpr(CPR0_PRIMBD0, reg); temp = (reg & PRBDV_MASK) >> 24; prbdv0 = temp ? temp : 8; if (prbdv0 != target_prbdv0) { reg &= ~PRBDV_MASK; reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24); - mtcpr(CPR0_PRIMBD, reg); + mtcpr(CPR0_PRIMBD0, reg); reset_needed = 1; } diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c index fa3bfc8..22ed5c2 100644 --- a/cpu/ppc4xx/miiphy.c +++ b/cpu/ppc4xx/miiphy.c @@ -195,7 +195,7 @@ unsigned int miiphy_getemac_offset(u8 addr) unsigned long eoffset; /* Need to find out which mdi port we're using */ - zmii = in_be32((void *)ZMII_FER); + zmii = in_be32((void *)ZMII0_FER); if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) /* using port 0 */ @@ -217,12 +217,12 @@ unsigned int miiphy_getemac_offset(u8 addr) /* None of the mdi ports are enabled! */ /* enable port 0 */ zmii |= ZMII_FER_MDI << ZMII_FER_V (0); - out_be32((void *)ZMII_FER, zmii); + out_be32((void *)ZMII0_FER, zmii); eoffset = 0; /* need to soft reset port 0 */ - zmii = in_be32((void *)EMAC_M0); - zmii |= EMAC_M0_SRST; - out_be32((void *)EMAC_M0, zmii); + zmii = in_be32((void *)EMAC0_MR0); + zmii |= EMAC_MR0_SRST; + out_be32((void *)EMAC0_MR0, zmii); } return (eoffset); @@ -243,19 +243,19 @@ unsigned int miiphy_getemac_offset(u8 addr) switch (addr) { #if defined(CONFIG_HAS_ETH1) && defined(CONFIG_GPCS_PHY1_ADDR) case CONFIG_GPCS_PHY1_ADDR: - if (addr == EMAC_M1_IPPA_GET(in_be32((void *)EMAC_M1 + 0x100))) + if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x100))) eoffset = 0x100; break; #endif #if defined(CONFIG_HAS_ETH2) && defined(CONFIG_GPCS_PHY2_ADDR) case CONFIG_GPCS_PHY2_ADDR: - if (addr == EMAC_M1_IPPA_GET(in_be32((void *)EMAC_M1 + 0x300))) + if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x300))) eoffset = 0x300; break; #endif #if defined(CONFIG_HAS_ETH3) && defined(CONFIG_GPCS_PHY3_ADDR) case CONFIG_GPCS_PHY3_ADDR: - if (addr == EMAC_M1_IPPA_GET(in_be32((void *)EMAC_M1 + 0x400))) + if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x400))) eoffset = 0x400; break; #endif @@ -278,9 +278,9 @@ static int emac_miiphy_wait(u32 emac_reg) /* wait for completion */ i = 0; do { - sta_reg = in_be32((void *)EMAC_STACR + emac_reg); + sta_reg = in_be32((void *)EMAC0_STACR + emac_reg); if (i++ > 5) { - debug("%s [%d]: Timeout! EMAC_STACR=0x%0x\n", __func__, + debug("%s [%d]: Timeout! EMAC0_STACR=0x%0x\n", __func__, __LINE__, sta_reg); return -1; } @@ -324,7 +324,7 @@ static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value) if (cmd == EMAC_STACR_WRITE) memcpy(&sta_reg, &value, 2); /* put in data */ - out_be32((void *)EMAC_STACR + emac_reg, sta_reg); + out_be32((void *)EMAC0_STACR + emac_reg, sta_reg); debug("%s [%d]: sta_reg=%08x\n", __func__, __LINE__, sta_reg); /* wait for completion */ @@ -349,7 +349,7 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, unsigned char reg, if (emac_miiphy_command(addr, reg, EMAC_STACR_READ, 0) != 0) return -1; - sta_reg = in_be32((void *)EMAC_STACR + emac_reg); + sta_reg = in_be32((void *)EMAC0_STACR + emac_reg); *value = sta_reg >> 16; return 0; diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index 988ba97..906face 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -334,7 +334,7 @@ void get_sys_info (sys_info_t *sysInfo) sysInfo->pllFbkDiv = temp ? temp : 32; lfdiv = reg & PLLD_LFBDV_MASK; - mfcpr(CPR0_OPBD, reg); + mfcpr(CPR0_OPBD0, reg); temp = (reg & OPBDDV_MASK) >> 24; sysInfo->pllOpbDiv = temp ? temp : 4; @@ -342,7 +342,7 @@ void get_sys_info (sys_info_t *sysInfo) temp = (reg & PERDV_MASK) >> 24; sysInfo->pllExtBusDiv = temp ? temp : 8; - mfcpr(CPR0_PRIMBD, reg); + mfcpr(CPR0_PRIMBD0, reg); temp = (reg & PRBDV_MASK) >> 24; prbdv0 = temp ? temp : 8; @@ -1050,7 +1050,7 @@ void get_sys_info (sys_info_t * sysInfo) /* * Determine OPBDV0 */ - mfcpr(CPR0_OPBD, tmp); + mfcpr(CPR0_OPBD0, tmp); tmp = (tmp >> 24) & 0x03; sysInfo->pllOpbDiv = (tmp == 0) ? 4 : tmp; |