diff options
author | Stefan Roese <sr@denx.de> | 2005-08-04 15:09:16 (GMT) |
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committer | Stefan Roese <sr@denx.de> | 2005-08-04 15:09:16 (GMT) |
commit | 17f50f22bc3f2d17258523f2ef3074e6ce1f7ffa (patch) | |
tree | 2c5d47cd55f487f0504458908d587e9bcd6963a6 /cpu | |
parent | 3e0bc4473add883fd68a49b7dab971191b943415 (diff) | |
download | u-boot-17f50f22bc3f2d17258523f2ef3074e6ce1f7ffa.tar.xz |
Add support for AMCC Bamboo PPC440EP eval board
Patch by Stefan Roese, 04 Aug 2005
Diffstat (limited to 'cpu')
-rw-r--r-- | cpu/ppc4xx/405gp_enet.c | 27 | ||||
-rw-r--r-- | cpu/ppc4xx/440gx_enet.c | 63 | ||||
-rw-r--r-- | cpu/ppc4xx/cpu.c | 4 | ||||
-rw-r--r-- | cpu/ppc4xx/spd_sdram.c | 16 | ||||
-rw-r--r-- | cpu/ppc4xx/start.S | 8 |
5 files changed, 68 insertions, 50 deletions
diff --git a/cpu/ppc4xx/405gp_enet.c b/cpu/ppc4xx/405gp_enet.c index 9c17e31..b60d122 100644 --- a/cpu/ppc4xx/405gp_enet.c +++ b/cpu/ppc4xx/405gp_enet.c @@ -166,7 +166,6 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) failsafe--; if (failsafe == 0) break; - } /* EMAC RESET */ @@ -223,18 +222,19 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #endif /* MAL RESET */ - mtdcr (malmcr, MAL_CR_MMSR); - /* wait for reset */ - while (mfdcr (malmcr) & MAL_CR_MMSR) { - }; + mtdcr (malmcr, MAL_CR_MMSR); + /* wait for reset */ + while (mfdcr (malmcr) & MAL_CR_MMSR) { + }; + #if defined(CONFIG_440_EP) || defined(CONFIG_440_GR) out32 (ZMII_FER, 0); udelay(100); /* set RII mode */ out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0); #elif defined(CONFIG_440) - /* set RMII mode */ - out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0); + /* set RMII mode */ + out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0); #endif /* CONFIG_440 */ /* MAL Channel RESET */ @@ -324,14 +324,11 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) (int) speed, (duplex == HALF) ? "HALF" : "FULL"); } -#if defined(CONFIG_440) - /* Errata 1.12: MAL_1 -- Disable MAL bursting */ - if( get_pvr() == PVR_440GP_RB) - mtdcr (malmcr, MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); - else -#else mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); -#endif + /* Errata 1.12: MAL_1 -- Disable MAL bursting */ + if (get_pvr() == PVR_440GP_RB) { + mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB); + } /* Free "old" buffers */ if (hw_p->alloc_tx_buf) @@ -418,6 +415,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) reg |= dev->enetaddr[5]; out32 (EMAC_IAL + hw_p->hw_addr, reg); + switch (devnum) { #if defined(CONFIG_NET_MULTI) case 1: @@ -498,7 +496,6 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); #endif - /* Frame gap set */ out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); diff --git a/cpu/ppc4xx/440gx_enet.c b/cpu/ppc4xx/440gx_enet.c index 24e6ef3..f4004fb 100644 --- a/cpu/ppc4xx/440gx_enet.c +++ b/cpu/ppc4xx/440gx_enet.c @@ -391,6 +391,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis) failsafe--; } +#if defined(CONFIG_440_GX) /* Whack the M1 register */ mode_reg = 0x0; mode_reg &= ~0x00000038; @@ -405,7 +406,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis) mode_reg |= EMAC_M1_OBCI_GT100; out32 (EMAC_M1 + hw_p->hw_addr, mode_reg); - +#endif /* defined(CONFIG_440_GX) */ /* wait for PHY to complete auto negotiation */ reg_short = 0; @@ -432,6 +433,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis) bis->bi_phynum[devnum] = reg; +#ifndef CONFIG_NO_PHY_RESET /* * Reset the phy, only if its the first time through * otherwise, just check the speeds & feeds @@ -441,35 +443,36 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis) #if defined(CONFIG_440_GX) #if defined(CONFIG_CIS8201_PHY) - /* - * Cicada 8201 PHY needs to have an extended register whacked - * for RGMII mode. - */ - if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) { - miiphy_write (reg, 23, 0x1200); /* - * Vitesse VSC8201/Cicada CIS8201 errata: - * Interoperability problem with Intel 82547EI phys - * This work around (provided by Vitesse) changes - * the default timer convergence from 8ms to 12ms + * Cicada 8201 PHY needs to have an extended register whacked + * for RGMII mode. */ - miiphy_write (reg, 0x1f, 0x2a30); - miiphy_write (reg, 0x08, 0x0200); - miiphy_write (reg, 0x1f, 0x52b5); - miiphy_write (reg, 0x02, 0x0004); - miiphy_write (reg, 0x01, 0x0671); - miiphy_write (reg, 0x00, 0x8fae); - miiphy_write (reg, 0x1f, 0x2a30); - miiphy_write (reg, 0x08, 0x0000); - miiphy_write (reg, 0x1f, 0x0000); - /* end Vitesse/Cicada errata */ - } + if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) { + miiphy_write (reg, 23, 0x1200); + /* + * Vitesse VSC8201/Cicada CIS8201 errata: + * Interoperability problem with Intel 82547EI phys + * This work around (provided by Vitesse) changes + * the default timer convergence from 8ms to 12ms + */ + miiphy_write (reg, 0x1f, 0x2a30); + miiphy_write (reg, 0x08, 0x0200); + miiphy_write (reg, 0x1f, 0x52b5); + miiphy_write (reg, 0x02, 0x0004); + miiphy_write (reg, 0x01, 0x0671); + miiphy_write (reg, 0x00, 0x8fae); + miiphy_write (reg, 0x1f, 0x2a30); + miiphy_write (reg, 0x08, 0x0000); + miiphy_write (reg, 0x1f, 0x0000); + /* end Vitesse/Cicada errata */ + } #endif #endif /* Start/Restart autonegotiation */ phy_setup_aneg (reg); udelay (1000); } +#endif /* CONFIG_NO_PHY_RESET */ miiphy_read (reg, PHY_BMSR, ®_short); @@ -538,14 +541,16 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis) } /* set the Mal configuration reg */ +#if defined(CONFIG_440_GX) + mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | + MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000); +#else + mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); /* Errata 1.12: MAL_1 -- Disable MAL bursting */ - if (get_pvr () == PVR_440GP_RB) - mtdcr (malmcr, - MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); - else - mtdcr (malmcr, - MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | - MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000); + if (get_pvr() == PVR_440GP_RB) { + mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB); + } +#endif /* Free "old" buffers */ if (hw_p->alloc_tx_buf) diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index ae45a23..3a4b5d0 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -152,7 +152,7 @@ int checkcpu (void) #endif #if defined(CONFIG_440) - puts ("AMCC PowerPC 440 "); + puts ("AMCC PowerPC 440"); switch(pvr) { case PVR_440GP_RB: puts("GP Rev. B"); @@ -195,7 +195,7 @@ int checkcpu (void) #endif default: - printf ("UNKNOWN (PVR=%08x)", pvr); + printf (" UNKNOWN (PVR=%08x)", pvr); break; } #endif diff --git a/cpu/ppc4xx/spd_sdram.c b/cpu/ppc4xx/spd_sdram.c index 520107a..e2eab62 100644 --- a/cpu/ppc4xx/spd_sdram.c +++ b/cpu/ppc4xx/spd_sdram.c @@ -1590,7 +1590,6 @@ unsigned long program_bxcr(unsigned long* dimm_populated, unsigned long num_dimm_banks) { unsigned long dimm_num; - unsigned long bxcr_num; unsigned long bank_base_addr; unsigned long bank_size_bytes; unsigned long cr; @@ -1601,6 +1600,8 @@ unsigned long program_bxcr(unsigned long* dimm_populated, unsigned char num_banks; unsigned char bank_size_id; +#ifndef CONFIG_BAMBOO + unsigned long bxcr_num; /* * Set the BxCR regs. First, wipe out the bank config registers. @@ -1609,11 +1610,16 @@ unsigned long program_bxcr(unsigned long* dimm_populated, mtdcr(memcfga, mem_b0cr + (bxcr_num << 2)); mtdcr(memcfgd, 0x00000000); } +#endif /* * reset the bank_base address */ +#ifndef CONFIG_BAMBOO bank_base_addr = CFG_SDRAM_BASE; +#else + bank_base_addr = CFG_SDRAM_ONBOARD_SIZE; +#endif for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { if (dimm_populated[dimm_num] == TRUE) { @@ -1691,7 +1697,11 @@ unsigned long program_bxcr(unsigned long* dimm_populated, +-----------------------------------------------------------------*/ if (dimm_num == 0) { for (i = 0; i < num_banks; i++) { +#ifndef CONFIG_BAMBOO mtdcr(memcfga, mem_b0cr + (i << 2)); +#else + mtdcr(memcfga, mem_b1cr + (i << 2)); +#endif temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK | SDRAM_BXCR_SDAM_MASK | @@ -1703,7 +1713,11 @@ unsigned long program_bxcr(unsigned long* dimm_populated, } } else { for (i = 0; i < num_banks; i++) { +#ifndef CONFIG_BAMBOO mtdcr(memcfga, mem_b2cr + (i << 2)); +#else + mtdcr(memcfga, mem_b3cr + (i << 2)); +#endif temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK | SDRAM_BXCR_SDAM_MASK | diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 3a8ff2b..788c71c 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -379,11 +379,13 @@ __440gx_msr_continue: li r0,0 #if defined(CONFIG_440_EP) || defined(CONFIG_440_GR) /* Clear Dcache to use as RAM */ - lis r3,CFG_INIT_RAM_ADDR@h - li r4,CFG_INIT_RAM_END@l + addis r3,r0,CFG_INIT_RAM_ADDR@h + ori r3,r3,CFG_INIT_RAM_ADDR@l + addis r4,r0,CFG_INIT_RAM_END@h + ori r4,r4,CFG_INIT_RAM_END@l rlwinm. r5,r4,0,27,31 rlwinm r5,r4,27,5,31 - beq ..d_ran + beq ..d_ran addi r5,r5,0x0001 ..d_ran: mtctr r5 |