diff options
author | wdenk <wdenk> | 2004-10-09 22:21:29 (GMT) |
---|---|---|
committer | wdenk <wdenk> | 2004-10-09 22:21:29 (GMT) |
commit | 1d9f410500f32b04b18b176386e77afacda7acfb (patch) | |
tree | c381f275ad04efac5da30ec72c14016b09437135 /cpu | |
parent | 3e01d75ff25b3668191beb86ab32cb2d1fb7f73b (diff) | |
download | u-boot-1d9f410500f32b04b18b176386e77afacda7acfb.tar.xz |
Patch by Steven Scholz, 16 Aug 2004:
- Introducing the concept of SoCs "./cpu/$(CPU)/$(SOC)"
- creating subdirs for SoCs ./cpu/arm920t/imx and ./cpu/arm920t/s3c24x0
- moving SoC specific code out of cpu/arm920t/ into cpu/arm920t/$(SOC)/
- moving drivers/s3c24x0_i2c.c and drivers/serial_imx.c out of drivers/
into cpu/arm920t/$(SOC)/
Diffstat (limited to 'cpu')
-rw-r--r-- | cpu/arm920t/Makefile | 6 | ||||
-rw-r--r-- | cpu/arm920t/imx/Makefile | 42 | ||||
-rw-r--r-- | cpu/arm920t/imx/generic.c (renamed from cpu/arm920t/imx_generic.c) | 0 | ||||
-rw-r--r-- | cpu/arm920t/imx/interrupts.c (renamed from cpu/arm920t/imx_interrupts.c) | 0 | ||||
-rw-r--r-- | cpu/arm920t/imx/serial.c | 201 | ||||
-rw-r--r-- | cpu/arm920t/imx/speed.c (renamed from cpu/arm920t/imx_speed.c) | 0 | ||||
-rw-r--r-- | cpu/arm920t/s3c24x0/Makefile | 43 | ||||
-rw-r--r-- | cpu/arm920t/s3c24x0/i2c.c | 447 | ||||
-rw-r--r-- | cpu/arm920t/s3c24x0/interrupts.c (renamed from cpu/arm920t/s3c24x0_interrupts.c) | 0 | ||||
-rw-r--r-- | cpu/arm920t/s3c24x0/serial.c (renamed from cpu/arm920t/s3c24x0_serial.c) | 0 | ||||
-rw-r--r-- | cpu/arm920t/s3c24x0/speed.c (renamed from cpu/arm920t/s3c24x0_speed.c) | 0 | ||||
-rw-r--r-- | cpu/arm920t/s3c24x0/usb_ohci.c (renamed from cpu/arm920t/usb_ohci.c) | 0 | ||||
-rw-r--r-- | cpu/arm920t/s3c24x0/usb_ohci.h (renamed from cpu/arm920t/usb_ohci.h) | 0 |
13 files changed, 734 insertions, 5 deletions
diff --git a/cpu/arm920t/Makefile b/cpu/arm920t/Makefile index 68a33d6..8f256e9 100644 --- a/cpu/arm920t/Makefile +++ b/cpu/arm920t/Makefile @@ -26,11 +26,7 @@ include $(TOPDIR)/config.mk LIB = lib$(CPU).a START = start.o -OBJS = cpu.o \ - imx_generic.o imx_interrupts.o imx_speed.o \ - interrupts.o \ - s3c24x0_interrupts.o s3c24x0_serial.o s3c24x0_speed.o \ - usb_ohci.o +OBJS = cpu.o interrupts.o all: .depend $(START) $(LIB) diff --git a/cpu/arm920t/imx/Makefile b/cpu/arm920t/imx/Makefile new file mode 100644 index 0000000..8865f82 --- /dev/null +++ b/cpu/arm920t/imx/Makefile @@ -0,0 +1,42 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(SOC).a + +OBJS = generic.o interrupts.o serial.o speed.o + +all: .depend $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/arm920t/imx_generic.c b/cpu/arm920t/imx/generic.c index aa7c8c1..aa7c8c1 100644 --- a/cpu/arm920t/imx_generic.c +++ b/cpu/arm920t/imx/generic.c diff --git a/cpu/arm920t/imx_interrupts.c b/cpu/arm920t/imx/interrupts.c index 12ae2fa..12ae2fa 100644 --- a/cpu/arm920t/imx_interrupts.c +++ b/cpu/arm920t/imx/interrupts.c diff --git a/cpu/arm920t/imx/serial.c b/cpu/arm920t/imx/serial.c new file mode 100644 index 0000000..9dbaa56 --- /dev/null +++ b/cpu/arm920t/imx/serial.c @@ -0,0 +1,201 @@ +/* + * (c) 2004 Sascha Hauer <sascha@saschahauer.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include <common.h> +#if defined (CONFIG_IMX) + +#include <asm/arch/imx-regs.h> + +#ifndef CONFIG_IMX_SERIAL_NONE + +#if defined CONFIG_IMX_SERIAL1 +#define UART_BASE IMX_UART1_BASE +#elif defined CONFIG_IMX_SERIAL2 +#define UART_BASE IMX_UART2_BASE +#else +#error "define CONFIG_IMX_SERIAL1, CONFIG_IMX_SERIAL2 or CONFIG_IMX_SERIAL_NONE" +#endif + +struct imx_serial { + volatile uint32_t urxd[16]; + volatile uint32_t utxd[16]; + volatile uint32_t ucr1; + volatile uint32_t ucr2; + volatile uint32_t ucr3; + volatile uint32_t ucr4; + volatile uint32_t ufcr; + volatile uint32_t usr1; + volatile uint32_t usr2; + volatile uint32_t uesc; + volatile uint32_t utim; + volatile uint32_t ubir; + volatile uint32_t ubmr; + volatile uint32_t ubrc; + volatile uint32_t bipr[4]; + volatile uint32_t bmpr[4]; + volatile uint32_t uts; +}; + +void serial_setbrg (void) +{ + serial_init(); +} + +extern void imx_gpio_mode(int gpio_mode); + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + * + */ +int serial_init (void) +{ + volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; +#ifdef CONFIG_IMX_SERIAL1 + imx_gpio_mode(PC11_PF_UART1_TXD); + imx_gpio_mode(PC12_PF_UART1_RXD); +#else + imx_gpio_mode(PB30_PF_UART2_TXD); + imx_gpio_mode(PB31_PF_UART2_RXD); +#endif + + /* Disable UART */ + base->ucr1 &= ~UCR1_UARTEN; + + /* Set to default POR state */ + + base->ucr1 = 0x00000004; + base->ucr2 = 0x00000000; + base->ucr3 = 0x00000000; + base->ucr4 = 0x00008040; + base->uesc = 0x0000002B; + base->utim = 0x00000000; + base->ubir = 0x00000000; + base->ubmr = 0x00000000; + base->uts = 0x00000000; + /* Set clocks */ + base->ucr4 |= UCR4_REF16; + + /* Configure FIFOs */ + base->ufcr = 0xa81; + + /* Set the numerator value minus one of the BRM ratio */ + base->ubir = (CONFIG_BAUDRATE / 100) - 1; + + /* Set the denominator value minus one of the BRM ratio */ + base->ubmr = 10000 - 1; + + /* Set to 8N1 */ + base->ucr2 &= ~UCR2_PREN; + base->ucr2 |= UCR2_WS; + base->ucr2 &= ~UCR2_STPB; + + /* Ignore RTS */ + base->ucr2 |= UCR2_IRTS; + + /* Enable UART */ + base->ucr1 |= UCR1_UARTEN | UCR1_UARTCLKEN; + + /* Enable FIFOs */ + base->ucr2 |= UCR2_SRST | UCR2_RXEN | UCR2_TXEN; + + /* Clear status flags */ + base->usr2 |= USR2_ADET | + USR2_DTRF | + USR2_IDLE | + USR2_IRINT | + USR2_WAKE | + USR2_RTSF | + USR2_BRCD | + USR2_ORE | + USR2_RDR; + + /* Clear status flags */ + base->usr1 |= USR1_PARITYERR | + USR1_RTSD | + USR1_ESCF | + USR1_FRAMERR | + USR1_AIRINT | + USR1_AWAKE; + return (0); +} + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. When the function is successful, the character read is + * written into its argument c. + */ +int serial_getc (void) +{ + volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; + unsigned char ch; + + while(base->uts & UTS_RXEMPTY); + + ch = (char)base->urxd[0]; + + return ch; +} + +#ifdef CONFIG_HWFLOW +static int hwflow = 0; /* turned off by default */ +int hwflow_onoff(int on) +{ +} +#endif + +/* + * Output a single byte to the serial port. + */ +void serial_putc (const char c) +{ + volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; + + /* Wait for Tx FIFO not full */ + while (base->uts & UTS_TXFULL); + + base->utxd[0] = c; + + /* If \n, also do \r */ + if (c == '\n') + serial_putc ('\r'); +} + +/* + * Test whether a character is in the RX buffer + */ +int serial_tstc (void) +{ + volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; + + /* If receive fifo is empty, return false */ + if (base->uts & UTS_RXEMPTY) + return 0; + return 1; +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} +#endif /* CONFIG_IMX_SERIAL_NONE */ +#endif /* defined CONFIG_IMX */ diff --git a/cpu/arm920t/imx_speed.c b/cpu/arm920t/imx/speed.c index 1e29698..1e29698 100644 --- a/cpu/arm920t/imx_speed.c +++ b/cpu/arm920t/imx/speed.c diff --git a/cpu/arm920t/s3c24x0/Makefile b/cpu/arm920t/s3c24x0/Makefile new file mode 100644 index 0000000..af9e4ef --- /dev/null +++ b/cpu/arm920t/s3c24x0/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(SOC).a + +OBJS = i2c.o interrupts.o serial.o speed.o \ + usb_ohci.o + +all: .depend $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/arm920t/s3c24x0/i2c.c b/cpu/arm920t/s3c24x0/i2c.c new file mode 100644 index 0000000..ef56cd1 --- /dev/null +++ b/cpu/arm920t/s3c24x0/i2c.c @@ -0,0 +1,447 @@ +/* + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, d.mueller@elsoft.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* This code should work for both the S3C2400 and the S3C2410 + * as they seem to have the same I2C controller inside. + * The different address mapping is handled by the s3c24xx.h files below. + */ + +#include <common.h> + +#ifdef CONFIG_DRIVER_S3C24X0_I2C + +#if defined(CONFIG_S3C2400) +#include <s3c2400.h> +#elif defined(CONFIG_S3C2410) +#include <s3c2410.h> +#endif +#include <i2c.h> + +#ifdef CONFIG_HARD_I2C + +#define I2C_WRITE 0 +#define I2C_READ 1 + +#define I2C_OK 0 +#define I2C_NOK 1 +#define I2C_NACK 2 +#define I2C_NOK_LA 3 /* Lost arbitration */ +#define I2C_NOK_TOUT 4 /* time out */ + +#define I2CSTAT_BSY 0x20 /* Busy bit */ +#define I2CSTAT_NACK 0x01 /* Nack bit */ +#define I2CCON_IRPND 0x10 /* Interrupt pending bit */ +#define I2C_MODE_MT 0xC0 /* Master Transmit Mode */ +#define I2C_MODE_MR 0x80 /* Master Receive Mode */ +#define I2C_START_STOP 0x20 /* START / STOP */ +#define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */ + +#define I2C_TIMEOUT 1 /* 1 second */ + + +static int GetI2CSDA(void) +{ + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + +#ifdef CONFIG_S3C2410 + return (gpio->GPEDAT & 0x8000) >> 15; +#endif +#ifdef CONFIG_S3C2400 + return (gpio->PGDAT & 0x0020) >> 5; +#endif +} + +#if 0 +static void SetI2CSDA(int x) +{ + rGPEDAT = (rGPEDAT & ~0x8000) | (x&1) << 15; +} +#endif + +static void SetI2CSCL(int x) +{ + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + +#ifdef CONFIG_S3C2410 + gpio->GPEDAT = (gpio->GPEDAT & ~0x4000) | (x&1) << 14; +#endif +#ifdef CONFIG_S3C2400 + gpio->PGDAT = (gpio->PGDAT & ~0x0040) | (x&1) << 6; +#endif +} + + +static int WaitForXfer (void) +{ + S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); + int i, status; + + i = I2C_TIMEOUT * 10000; + status = i2c->IICCON; + while ((i > 0) && !(status & I2CCON_IRPND)) { + udelay (100); + status = i2c->IICCON; + i--; + } + + return (status & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; +} + +static int IsACK (void) +{ + S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); + + return (!(i2c->IICSTAT & I2CSTAT_NACK)); +} + +static void ReadWriteByte (void) +{ + S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); + + i2c->IICCON &= ~I2CCON_IRPND; +} + +void i2c_init (int speed, int slaveadd) +{ + S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); + S3C24X0_GPIO *const gpio = S3C24X0_GetBase_GPIO (); + ulong freq, pres = 16, div; + int i, status; + + /* wait for some time to give previous transfer a chance to finish */ + + i = I2C_TIMEOUT * 1000; + status = i2c->IICSTAT; + while ((i > 0) && (status & I2CSTAT_BSY)) { + udelay (1000); + status = i2c->IICSTAT; + i--; + } + + if ((status & I2CSTAT_BSY) || GetI2CSDA () == 0) { +#ifdef CONFIG_S3C2410 + ulong old_gpecon = gpio->GPECON; +#endif +#ifdef CONFIG_S3C2400 + ulong old_gpecon = gpio->PGCON; +#endif + /* bus still busy probably by (most) previously interrupted transfer */ + +#ifdef CONFIG_S3C2410 + /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */ + gpio->GPECON = (gpio->GPECON & ~0xF0000000) | 0x10000000; +#endif +#ifdef CONFIG_S3C2400 + /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */ + gpio->PGCON = (gpio->PGCON & ~0x00003c00) | 0x00000c00; +#endif + + /* toggle I2CSCL until bus idle */ + SetI2CSCL (0); + udelay (1000); + i = 10; + while ((i > 0) && (GetI2CSDA () != 1)) { + SetI2CSCL (1); + udelay (1000); + SetI2CSCL (0); + udelay (1000); + i--; + } + SetI2CSCL (1); + udelay (1000); + + /* restore pin functions */ +#ifdef CONFIG_S3C2410 + gpio->GPECON = old_gpecon; +#endif +#ifdef CONFIG_S3C2400 + gpio->PGCON = old_gpecon; +#endif + } + + /* calculate prescaler and divisor values */ + freq = get_PCLK (); + if ((freq / pres / (16 + 1)) > speed) + /* set prescaler to 512 */ + pres = 512; + + div = 0; + while ((freq / pres / (div + 1)) > speed) + div++; + + /* set prescaler, divisor according to freq, also set + * ACKGEN, IRQ */ + i2c->IICCON = (div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0); + + /* init to SLAVE REVEIVE and set slaveaddr */ + i2c->IICSTAT = 0; + i2c->IICADD = slaveadd; + /* program Master Transmit (and implicit STOP) */ + i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA; + +} + +/* + * cmd_type is 0 for write, 1 for read. + * + * addr_len can take any value from 0-255, it is only limited + * by the char, we could make it larger if needed. If it is + * 0 we skip the address write cycle. + */ +static +int i2c_transfer (unsigned char cmd_type, + unsigned char chip, + unsigned char addr[], + unsigned char addr_len, + unsigned char data[], unsigned short data_len) +{ + S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); + int i, status, result; + + if (data == 0 || data_len == 0) { + /*Don't support data transfer of no length or to address 0 */ + printf ("i2c_transfer: bad call\n"); + return I2C_NOK; + } + + /* Check I2C bus idle */ + i = I2C_TIMEOUT * 1000; + status = i2c->IICSTAT; + while ((i > 0) && (status & I2CSTAT_BSY)) { + udelay (1000); + status = i2c->IICSTAT; + i--; + } + + if (status & I2CSTAT_BSY) + return I2C_NOK_TOUT; + + i2c->IICCON |= 0x80; + result = I2C_OK; + + switch (cmd_type) { + case I2C_WRITE: + if (addr && addr_len) { + i2c->IICDS = chip; + /* send START */ + i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP; + i = 0; + while ((i < addr_len) && (result == I2C_OK)) { + result = WaitForXfer (); + i2c->IICDS = addr[i]; + ReadWriteByte (); + i++; + } + i = 0; + while ((i < data_len) && (result == I2C_OK)) { + result = WaitForXfer (); + i2c->IICDS = data[i]; + ReadWriteByte (); + i++; + } + } else { + i2c->IICDS = chip; + /* send START */ + i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP; + i = 0; + while ((i < data_len) && (result = I2C_OK)) { + result = WaitForXfer (); + i2c->IICDS = data[i]; + ReadWriteByte (); + i++; + } + } + + if (result == I2C_OK) + result = WaitForXfer (); + + /* send STOP */ + i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA; + ReadWriteByte (); + break; + + case I2C_READ: + if (addr && addr_len) { + i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA; + i2c->IICDS = chip; + /* send START */ + i2c->IICSTAT |= I2C_START_STOP; + result = WaitForXfer (); + if (IsACK ()) { + i = 0; + while ((i < addr_len) && (result == I2C_OK)) { + i2c->IICDS = addr[i]; + ReadWriteByte (); + result = WaitForXfer (); + i++; + } + + i2c->IICDS = chip; + /* resend START */ + i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA | + I2C_START_STOP; + ReadWriteByte (); + result = WaitForXfer (); + i = 0; + while ((i < data_len) && (result == I2C_OK)) { + /* disable ACK for final READ */ + if (i == data_len - 1) + i2c->IICCON &= ~0x80; + ReadWriteByte (); + result = WaitForXfer (); + data[i] = i2c->IICDS; + i++; + } + } else { + result = I2C_NACK; + } + + } else { + i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA; + i2c->IICDS = chip; + /* send START */ + i2c->IICSTAT |= I2C_START_STOP; + result = WaitForXfer (); + + if (IsACK ()) { + i = 0; + while ((i < data_len) && (result == I2C_OK)) { + /* disable ACK for final READ */ + if (i == data_len - 1) + i2c->IICCON &= ~0x80; + ReadWriteByte (); + result = WaitForXfer (); + data[i] = i2c->IICDS; + i++; + } + } else { + result = I2C_NACK; + } + } + + /* send STOP */ + i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA; + ReadWriteByte (); + break; + + default: + printf ("i2c_transfer: bad call\n"); + result = I2C_NOK; + break; + } + + return (result); +} + +int i2c_probe (uchar chip) +{ + uchar buf[1]; + + buf[0] = 0; + + /* + * What is needed is to send the chip address and verify that the + * address was <ACK>ed (i.e. there was a chip at that address which + * drove the data line low). + */ + return (i2c_transfer (I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK); +} + +int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + uchar xaddr[4]; + int ret; + + if (alen > 4) { + printf ("I2C read: addr len %d not supported\n", alen); + return 1; + } + + if (alen > 0) { + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + } + +#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of + * address and the extra bits end up in the "chip address" + * bit slots. This makes a 24WC08 (1Kbyte) chip look like + * four 256 byte chips. + * + * Note that we consider the length of the address field to + * still be one byte because the extra address bits are + * hidden in the chip address. + */ + if (alen > 0) + chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); +#endif + if ((ret = + i2c_transfer (I2C_READ, chip << 1, &xaddr[4 - alen], alen, + buffer, len)) != 0) { + printf ("I2c read: failed %d\n", ret); + return 1; + } + return 0; +} + +int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + uchar xaddr[4]; + + if (alen > 4) { + printf ("I2C write: addr len %d not supported\n", alen); + return 1; + } + + if (alen > 0) { + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + } +#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of + * address and the extra bits end up in the "chip address" + * bit slots. This makes a 24WC08 (1Kbyte) chip look like + * four 256 byte chips. + * + * Note that we consider the length of the address field to + * still be one byte because the extra address bits are + * hidden in the chip address. + */ + if (alen > 0) + chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); +#endif + return (i2c_transfer + (I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer, + len) != 0); +} +#endif /* CONFIG_HARD_I2C */ + +#endif /* CONFIG_DRIVER_S3C24X0_I2C */ diff --git a/cpu/arm920t/s3c24x0_interrupts.c b/cpu/arm920t/s3c24x0/interrupts.c index 92298b0..92298b0 100644 --- a/cpu/arm920t/s3c24x0_interrupts.c +++ b/cpu/arm920t/s3c24x0/interrupts.c diff --git a/cpu/arm920t/s3c24x0_serial.c b/cpu/arm920t/s3c24x0/serial.c index 8327443..8327443 100644 --- a/cpu/arm920t/s3c24x0_serial.c +++ b/cpu/arm920t/s3c24x0/serial.c diff --git a/cpu/arm920t/s3c24x0_speed.c b/cpu/arm920t/s3c24x0/speed.c index e0dca62..e0dca62 100644 --- a/cpu/arm920t/s3c24x0_speed.c +++ b/cpu/arm920t/s3c24x0/speed.c diff --git a/cpu/arm920t/usb_ohci.c b/cpu/arm920t/s3c24x0/usb_ohci.c index 6f4a9f7..6f4a9f7 100644 --- a/cpu/arm920t/usb_ohci.c +++ b/cpu/arm920t/s3c24x0/usb_ohci.c diff --git a/cpu/arm920t/usb_ohci.h b/cpu/arm920t/s3c24x0/usb_ohci.h index fab0e65..fab0e65 100644 --- a/cpu/arm920t/usb_ohci.h +++ b/cpu/arm920t/s3c24x0/usb_ohci.h |