diff options
author | wdenk <wdenk> | 2004-08-01 22:48:16 (GMT) |
---|---|---|
committer | wdenk <wdenk> | 2004-08-01 22:48:16 (GMT) |
commit | 281e00a3be453a169d854f824a460359d10f92bb (patch) | |
tree | 43dab398f1d6f601bb44df108427f7e0c611d68d /cpu | |
parent | cfca5e604d5692f081cc1a9185ca5dc6dc77599d (diff) | |
download | u-boot-281e00a3be453a169d854f824a460359d10f92bb.tar.xz |
* Code cleanup
* Patch by Sascha Hauer, 28 Jun:
- add generic support for Motorola i.MX architecture
- add support for mx1ads, mx1fs2 and scb9328 boards
* Patches by Marc Leeman, 23 Jul 2004:
- Add define for the PCI/Memory Buffer Configuration Register
- corrected comments in cpu/mpc824x/cpu_init.c
* Add support for multiple serial interfaces
(for example to allow modem dial-in / dial-out)
Diffstat (limited to 'cpu')
-rw-r--r-- | cpu/arm720t/cpu.c | 2 | ||||
-rw-r--r-- | cpu/arm920t/Makefile | 6 | ||||
-rw-r--r-- | cpu/arm920t/imx_generic.c | 90 | ||||
-rw-r--r-- | cpu/arm920t/imx_interrupts.c | 117 | ||||
-rw-r--r-- | cpu/arm920t/imx_speed.c | 102 | ||||
-rw-r--r-- | cpu/arm920t/interrupts.c | 143 | ||||
-rw-r--r-- | cpu/arm920t/s3c24x0_interrupts.c | 180 | ||||
-rw-r--r-- | cpu/arm920t/s3c24x0_serial.c (renamed from cpu/arm920t/serial.c) | 34 | ||||
-rw-r--r-- | cpu/arm920t/s3c24x0_speed.c (renamed from cpu/arm920t/speed.c) | 6 | ||||
-rw-r--r-- | cpu/arm920t/start.S | 24 | ||||
-rw-r--r-- | cpu/mc9328/Makefile | 43 | ||||
-rw-r--r-- | cpu/mc9328/config.mk | 27 | ||||
-rw-r--r-- | cpu/mc9328/cpu.c | 183 | ||||
-rw-r--r-- | cpu/mc9328/interrupts.c | 249 | ||||
-rw-r--r-- | cpu/mc9328/serial.c | 133 | ||||
-rw-r--r-- | cpu/mc9328/start.S | 388 | ||||
-rw-r--r-- | cpu/mpc824x/cpu_init.c | 6 | ||||
-rw-r--r-- | cpu/mpc85xx/speed.c | 1 | ||||
-rw-r--r-- | cpu/mpc8xx/scc.c | 6 | ||||
-rw-r--r-- | cpu/mpc8xx/serial.c | 234 | ||||
-rw-r--r-- | cpu/mpc8xx/spi.c | 10 |
21 files changed, 688 insertions, 1296 deletions
diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c index 58eab4e..ef3fbf3 100644 --- a/cpu/arm720t/cpu.c +++ b/cpu/arm720t/cpu.c @@ -41,8 +41,6 @@ int cpu_init (void) * setup up stacks if necessary */ #ifdef CONFIG_USE_IRQ - DECLARE_GLOBAL_DATA_PTR; - IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; #endif diff --git a/cpu/arm920t/Makefile b/cpu/arm920t/Makefile index 605adf3..68a33d6 100644 --- a/cpu/arm920t/Makefile +++ b/cpu/arm920t/Makefile @@ -26,7 +26,11 @@ include $(TOPDIR)/config.mk LIB = lib$(CPU).a START = start.o -OBJS = serial.o interrupts.o cpu.o speed.o usb_ohci.o +OBJS = cpu.o \ + imx_generic.o imx_interrupts.o imx_speed.o \ + interrupts.o \ + s3c24x0_interrupts.o s3c24x0_serial.o s3c24x0_speed.o \ + usb_ohci.o all: .depend $(START) $(LIB) diff --git a/cpu/arm920t/imx_generic.c b/cpu/arm920t/imx_generic.c new file mode 100644 index 0000000..aa7c8c1 --- /dev/null +++ b/cpu/arm920t/imx_generic.c @@ -0,0 +1,90 @@ +/* + * arch/arm/mach-imx/generic.c + * + * author: Sascha Hauer + * Created: april 20th, 2004 + * Copyright: Synertronixx GmbH + * + * Common code for i.MX machines + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include <common.h> + +#ifdef CONFIG_IMX + +#include <asm/arch/imx-regs.h> + +void imx_gpio_mode(int gpio_mode) +{ + unsigned int pin = gpio_mode & GPIO_PIN_MASK; + unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> 5; + unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> 10; + unsigned int tmp; + + /* Pullup enable */ + if(gpio_mode & GPIO_PUEN) + PUEN(port) |= (1<<pin); + else + PUEN(port) &= ~(1<<pin); + + /* Data direction */ + if(gpio_mode & GPIO_OUT) + DDIR(port) |= 1<<pin; + else + DDIR(port) &= ~(1<<pin); + + /* Primary / alternate function */ + if(gpio_mode & GPIO_AF) + GPR(port) |= (1<<pin); + else + GPR(port) &= ~(1<<pin); + + /* use as gpio? */ + if( ocr == 3 ) + GIUS(port) |= (1<<pin); + else + GIUS(port) &= ~(1<<pin); + + /* Output / input configuration */ + /* FIXME: I'm not very sure about OCR and ICONF, someone + * should have a look over it + */ + if(pin<16) { + tmp = OCR1(port); + tmp &= ~( 3<<(pin*2)); + tmp |= (ocr << (pin*2)); + OCR1(port) = tmp; + + if( gpio_mode & GPIO_AOUT ) + ICONFA1(port) &= ~( 3<<(pin*2)); + if( gpio_mode & GPIO_BOUT ) + ICONFB1(port) &= ~( 3<<(pin*2)); + } else { + tmp = OCR2(port); + tmp &= ~( 3<<((pin-16)*2)); + tmp |= (ocr << ((pin-16)*2)); + OCR2(port) = tmp; + + if( gpio_mode & GPIO_AOUT ) + ICONFA2(port) &= ~( 3<<((pin-16)*2)); + if( gpio_mode & GPIO_BOUT ) + ICONFB2(port) &= ~( 3<<((pin-16)*2)); + } +} + +#endif /* CONFIG_IMX */ diff --git a/cpu/arm920t/imx_interrupts.c b/cpu/arm920t/imx_interrupts.c new file mode 100644 index 0000000..12ae2fa --- /dev/null +++ b/cpu/arm920t/imx_interrupts.c @@ -0,0 +1,117 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke <azu@sysgo.de> + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#if defined (CONFIG_IMX) + +#include <arm920t.h> +#include <asm/arch/imx-regs.h> + +int interrupt_init (void) +{ + int i; + /* setup GP Timer 1 */ + TCTL1 = TCTL_SWR; + for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */ + TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */ + TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */ + + reset_timer_masked(); + + return (0); +} + +/* + * timer without interrupts + */ + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked (); +} + +void set_timer (ulong t) +{ + /* nop */ +} + +void reset_timer_masked (void) +{ + TCTL1 &= ~TCTL_TEN; + TCTL1 |= TCTL_TEN; /* Enable timer */ +} + +ulong get_timer_masked (void) +{ + return TCN1; +} + +void udelay_masked (unsigned long usec) +{ + ulong start = get_timer_masked(); + + while (get_timer_masked () - start < usec ) + /*NOP*/; +} + +void udelay (unsigned long usec) +{ + udelay_masked(usec); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + ulong tbclk; + + tbclk = CFG_HZ; + + return tbclk; +} + +#endif /* defined (CONFIG_IMX) */ diff --git a/cpu/arm920t/imx_speed.c b/cpu/arm920t/imx_speed.c new file mode 100644 index 0000000..1e29698 --- /dev/null +++ b/cpu/arm920t/imx_speed.c @@ -0,0 +1,102 @@ +/* + * + * (c) 2004 Sascha Hauer <sascha@saschahauer.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <common.h> +#if defined (CONFIG_IMX) + +#include <asm/arch/imx-regs.h> + +/* ------------------------------------------------------------------------- */ +/* NOTE: This describes the proper use of this file. + * + * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL. + * SH FIXME: 16780000 in our case + * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of + * the specified bus in HZ. + */ +/* ------------------------------------------------------------------------- */ + +ulong get_systemPLLCLK(void) +{ + /* FIXME: We assume System_SEL = 0 here */ + u32 spctl0 = SPCTL0; + u32 mfi = (spctl0 >> 10) & 0xf; + u32 mfn = spctl0 & 0x3f; + u32 mfd = (spctl0 >> 16) & 0x3f; + u32 pd = (spctl0 >> 26) & 0xf; + + mfi = mfi<=5 ? 5 : mfi; + + return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1); +} + +ulong get_mcuPLLCLK(void) +{ + /* FIXME: We assume System_SEL = 0 here */ + u32 mpctl0 = MPCTL0; + u32 mfi = (mpctl0 >> 10) & 0xf; + u32 mfn = mpctl0 & 0x3f; + u32 mfd = (mpctl0 >> 16) & 0x3f; + u32 pd = (mpctl0 >> 26) & 0xf; + + mfi = mfi<=5 ? 5 : mfi; + + return (2*(CONFIG_SYS_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1); +} + +ulong get_FCLK(void) +{ + return (( CSCR>>15)&1) ? get_mcuPLLCLK()>>1 : get_mcuPLLCLK(); +} + +/* return HCLK frequency */ +ulong get_HCLK(void) +{ + u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1; + printf("bclkdiv: %d\n", bclkdiv); + return get_systemPLLCLK() / bclkdiv; +} + +/* return BCLK frequency */ +ulong get_BCLK(void) +{ + return get_HCLK(); +} + +ulong get_PERCLK1(void) +{ + return get_systemPLLCLK() / (((PCDR) & 0xf)+1); +} + +ulong get_PERCLK2(void) +{ + return get_systemPLLCLK() / (((PCDR>>4) & 0xf)+1); +} + +ulong get_PERCLK3(void) +{ + return get_systemPLLCLK() / (((PCDR>>16) & 0x7f)+1); +} + +#endif /* defined (CONFIG_IMX) */ diff --git a/cpu/arm920t/interrupts.c b/cpu/arm920t/interrupts.c index 521c4f4..ea58f15 100644 --- a/cpu/arm920t/interrupts.c +++ b/cpu/arm920t/interrupts.c @@ -30,25 +30,11 @@ */ #include <common.h> -#include <arm920t.h> -#if defined(CONFIG_S3C2400) -#include <s3c2400.h> -#elif defined(CONFIG_S3C2410) -#include <s3c2410.h> -#endif +#include <arm920t.h> #include <asm/proc-armv/ptrace.h> extern void reset_cpu(ulong addr); -int timer_load_val = 0; - -/* macro to read the 16 bit timer */ -static inline ulong READ_TIMER(void) -{ - S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); - - return (timers->TCNTO4 & 0xffff); -} #ifdef CONFIG_USE_IRQ /* enable IRQ interrupts */ @@ -182,130 +168,3 @@ void do_irq (struct pt_regs *pt_regs) show_regs (pt_regs); bad_mode (); } - -static ulong timestamp; -static ulong lastdec; - -int interrupt_init (void) -{ - S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); - - /* use PWM Timer 4 because it has no output */ - /* prescaler for Timer 4 is 16 */ - timers->TCFG0 = 0x0f00; - if (timer_load_val == 0) - { - /* - * for 10 ms clock period @ PCLK with 4 bit divider = 1/2 - * (default) and prescaler = 16. Should be 10390 - * @33.25MHz and 15625 @ 50 MHz - */ - timer_load_val = get_PCLK()/(2 * 16 * 100); - } - /* load value for 10 ms timeout */ - lastdec = timers->TCNTB4 = timer_load_val; - /* auto load, manual update of Timer 4 */ - timers->TCON = (timers->TCON & ~0x0700000) | 0x600000; - /* auto load, start Timer 4 */ - timers->TCON = (timers->TCON & ~0x0700000) | 0x500000; - timestamp = 0; - - return (0); -} - -/* - * timer without interrupts - */ - -void reset_timer (void) -{ - reset_timer_masked (); -} - -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -void set_timer (ulong t) -{ - timestamp = t; -} - -void udelay (unsigned long usec) -{ - ulong tmo; - ulong start = get_timer(0); - - tmo = usec / 1000; - tmo *= (timer_load_val * 100); - tmo /= 1000; - - while ((ulong)(get_timer_masked () - start) < tmo) - /*NOP*/; -} - -void reset_timer_masked (void) -{ - /* reset time */ - lastdec = READ_TIMER(); - timestamp = 0; -} - -ulong get_timer_masked (void) -{ - ulong now = READ_TIMER(); - - if (lastdec >= now) { - /* normal mode */ - timestamp += lastdec - now; - } else { - /* we have an overflow ... */ - timestamp += lastdec + timer_load_val - now; - } - lastdec = now; - - return timestamp; -} - -void udelay_masked (unsigned long usec) -{ - ulong tmo; - - tmo = usec / 1000; - tmo *= (timer_load_val * 100); - tmo /= 1000; - - reset_timer_masked (); - - while (get_timer_masked () < tmo) - /*NOP*/; -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - -#if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB) - tbclk = timer_load_val * 100; -#elif defined(CONFIG_SMDK2410) || defined(CONFIG_VCMA9) - tbclk = CFG_HZ; -#else -# error "tbclk not configured" -#endif - - return tbclk; -} diff --git a/cpu/arm920t/s3c24x0_interrupts.c b/cpu/arm920t/s3c24x0_interrupts.c new file mode 100644 index 0000000..92298b0 --- /dev/null +++ b/cpu/arm920t/s3c24x0_interrupts.c @@ -0,0 +1,180 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke <azu@sysgo.de> + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) + +#include <arm920t.h> +#if defined(CONFIG_S3C2400) +#include <s3c2400.h> +#elif defined(CONFIG_S3C2410) +#include <s3c2410.h> +#endif + +extern void reset_cpu(ulong addr); +int timer_load_val = 0; + +/* macro to read the 16 bit timer */ +static inline ulong READ_TIMER(void) +{ + S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); + + return (timers->TCNTO4 & 0xffff); +} + +static ulong timestamp; +static ulong lastdec; + +int interrupt_init (void) +{ + S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); + + /* use PWM Timer 4 because it has no output */ + /* prescaler for Timer 4 is 16 */ + timers->TCFG0 = 0x0f00; + if (timer_load_val == 0) + { + /* + * for 10 ms clock period @ PCLK with 4 bit divider = 1/2 + * (default) and prescaler = 16. Should be 10390 + * @33.25MHz and 15625 @ 50 MHz + */ + timer_load_val = get_PCLK()/(2 * 16 * 100); + } + /* load value for 10 ms timeout */ + lastdec = timers->TCNTB4 = timer_load_val; + /* auto load, manual update of Timer 4 */ + timers->TCON = (timers->TCON & ~0x0700000) | 0x600000; + /* auto load, start Timer 4 */ + timers->TCON = (timers->TCON & ~0x0700000) | 0x500000; + timestamp = 0; + + return (0); +} + +/* + * timer without interrupts + */ + +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +void udelay (unsigned long usec) +{ + ulong tmo; + ulong start = get_timer(0); + + tmo = usec / 1000; + tmo *= (timer_load_val * 100); + tmo /= 1000; + + while ((ulong)(get_timer_masked () - start) < tmo) + /*NOP*/; +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastdec = READ_TIMER(); + timestamp = 0; +} + +ulong get_timer_masked (void) +{ + ulong now = READ_TIMER(); + + if (lastdec >= now) { + /* normal mode */ + timestamp += lastdec - now; + } else { + /* we have an overflow ... */ + timestamp += lastdec + timer_load_val - now; + } + lastdec = now; + + return timestamp; +} + +void udelay_masked (unsigned long usec) +{ + ulong tmo; + + tmo = usec / 1000; + tmo *= (timer_load_val * 100); + tmo /= 1000; + + reset_timer_masked (); + + while (get_timer_masked () < tmo) + /*NOP*/; +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + ulong tbclk; + +#if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB) + tbclk = timer_load_val * 100; +#elif defined(CONFIG_SMDK2410) || defined(CONFIG_VCMA9) + tbclk = CFG_HZ; +#else +# error "tbclk not configured" +#endif + + return tbclk; +} + +#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */ diff --git a/cpu/arm920t/serial.c b/cpu/arm920t/s3c24x0_serial.c index 1749e82..8327443 100644 --- a/cpu/arm920t/serial.c +++ b/cpu/arm920t/s3c24x0_serial.c @@ -1,24 +1,26 @@ - /* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * */ #include <common.h> +#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) + #if defined(CONFIG_S3C2400) || defined(CONFIG_TRAB) #include <s3c2400.h> #elif defined(CONFIG_S3C2410) @@ -176,3 +178,5 @@ serial_puts (const char *s) serial_putc (*s++); } } + +#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */ diff --git a/cpu/arm920t/speed.c b/cpu/arm920t/s3c24x0_speed.c index 1f43543..e0dca62 100644 --- a/cpu/arm920t/speed.c +++ b/cpu/arm920t/s3c24x0_speed.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2001-2002 + * (C) Copyright 2001-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2002 @@ -30,6 +30,8 @@ */ #include <common.h> +#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) + #if defined(CONFIG_S3C2400) #include <s3c2400.h> #elif defined(CONFIG_S3C2410) @@ -95,3 +97,5 @@ ulong get_UCLK(void) { return(get_PLLCLK(UPLL)); } + +#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */ diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S index 0e372d0..78c470d 100644 --- a/cpu/arm920t/start.S +++ b/cpu/arm920t/start.S @@ -118,20 +118,17 @@ reset: /* turn off the watchdog */ #if defined(CONFIG_S3C2400) -#define pWTCON 0x15300000 -/* Interupt-Controller base addresses */ -#define INTMSK 0x14400008 -/* clock divisor register */ -#define CLKDIVN 0x14800014 +# define pWTCON 0x15300000 +# define INTMSK 0x14400008 /* Interupt-Controller base addresses */ +# define CLKDIVN 0x14800014 /* clock divisor register */ #elif defined(CONFIG_S3C2410) -#define pWTCON 0x53000000 -/* Interupt-Controller base addresses */ -#define INTMSK 0x4A000008 -#define INTSUBMSK 0x4A00001C -/* clock divisor register */ -#define CLKDIVN 0x4C000014 +# define pWTCON 0x53000000 +# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ +# define INTSUBMSK 0x4A00001C +# define CLKDIVN 0x4C000014 /* clock divisor register */ #endif +#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) ldr r0, =pWTCON mov r1, #0x0 str r1, [r0] @@ -142,17 +139,18 @@ reset: mov r1, #0xffffffff ldr r0, =INTMSK str r1, [r0] -#if defined(CONFIG_S3C2410) +# if defined(CONFIG_S3C2410) ldr r1, =0x3ff ldr r0, =INTSUBMSK str r1, [r0] -#endif +# endif /* FCLK:HCLK:PCLK = 1:2:4 */ /* default FCLK is 120 MHz ! */ ldr r0, =CLKDIVN mov r1, #3 str r1, [r0] +#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */ /* * we do sys-critical inits only at reboot, diff --git a/cpu/mc9328/Makefile b/cpu/mc9328/Makefile deleted file mode 100644 index fccc6ab..0000000 --- a/cpu/mc9328/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(CPU).a - -START = start.o -OBJS = serial.o interrupts.o cpu.o - -all: .depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/mc9328/config.mk b/cpu/mc9328/config.mk deleted file mode 100644 index cef7d26..0000000 --- a/cpu/mc9328/config.mk +++ /dev/null @@ -1,27 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, <gj@denx.de> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -mshort-load-bytes -msoft-float - -PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 diff --git a/cpu/mc9328/cpu.c b/cpu/mc9328/cpu.c deleted file mode 100644 index 2a2b578..0000000 --- a/cpu/mc9328/cpu.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * CPU specific code - */ - -#include <common.h> -#include <command.h> -#include <arm920t.h> - -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1 (void) -{ - unsigned long value; - - __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); - -#ifdef MMU_DEBUG - printf ("p15/c1 is = %08lx\n", value); -#endif - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1 (unsigned long value) -{ -#ifdef MMU_DEBUG - printf ("write %08lx to p15/c1\n", value); -#endif - __asm__ __volatile__( - "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" - : - : "r" (value) - : "memory"); - - read_p15_c1 (); -} - -static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++); -} - -/* See also ARM Ref. Man. */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_DC (1<<2) /* dcache off/on */ -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_IC (1<<12) /* icache off/on */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ -#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ - -int cpu_init (void) -{ - /* - * setup up stacks if necessary - */ -#ifdef CONFIG_USE_IRQ - DECLARE_GLOBAL_DATA_PTR; - - IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; - FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; -#endif - return 0; -} - -int cleanup_before_linux (void) -{ - /* - * this function is called just before we call linux - * it prepares the processor for linux - * - * we turn off caches etc ... - */ - - unsigned long i; - - disable_interrupts (); - - /* turn off I/D-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(C1_DC | C1_IC); - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - - /* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); - return (0); -} - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - extern void reset_cpu (ulong addr); - - disable_interrupts (); - reset_cpu (0); - /*NOTREACHED*/ - return (0); -} - -void icache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg | C1_IC); -} - -void icache_disable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_IC); -} - -int icache_status (void) -{ - return (read_p15_c1 () & C1_IC) != 0; -} - -#ifdef USE_920T_MMU -/* It makes no sense to use the dcache if the MMU is not enabled */ -void dcache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg | C1_DC); -} - -void dcache_disable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - reg &= ~C1_DC; - write_p15_c1 (reg); -} - -int dcache_status (void) -{ - return (read_p15_c1 () & C1_DC) != 0; -} -#endif diff --git a/cpu/mc9328/interrupts.c b/cpu/mc9328/interrupts.c deleted file mode 100644 index 2407db6..0000000 --- a/cpu/mc9328/interrupts.c +++ /dev/null @@ -1,249 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <arm920t.h> -#include <mc9328.h> - -#include <asm/proc-armv/ptrace.h> - -extern void reset_cpu(ulong addr); -int timer_load_val = 0; - -#ifdef CONFIG_USE_IRQ -/* enable IRQ interrupts */ -void enable_interrupts (void) -{ - unsigned long temp; - __asm__ __volatile__("mrs %0, cpsr\n" - "bic %0, %0, #0x80\n" - "msr cpsr_c, %0" - : "=r" (temp) - : - : "memory"); -} - - -/* - * disable IRQ/FIQ interrupts - * returns true if interrupts had been enabled before we disabled them - */ -int disable_interrupts (void) -{ - unsigned long old,temp; - __asm__ __volatile__("mrs %0, cpsr\n" - "orr %1, %0, #0xc0\n" - "msr cpsr_c, %1" - : "=r" (old), "=r" (temp) - : - : "memory"); - return (old & 0x80) == 0; -} -#else -void enable_interrupts (void) -{ - return; -} -int disable_interrupts (void) -{ - return 0; -} -#endif - - -void bad_mode (void) -{ - panic ("Resetting CPU ...\n"); - reset_cpu (0); -} - -void show_regs (struct pt_regs *regs) -{ - unsigned long flags; - const char *processor_modes[] = { - "USER_26", "FIQ_26", "IRQ_26", "SVC_26", - "UK4_26", "UK5_26", "UK6_26", "UK7_26", - "UK8_26", "UK9_26", "UK10_26", "UK11_26", - "UK12_26", "UK13_26", "UK14_26", "UK15_26", - "USER_32", "FIQ_32", "IRQ_32", "SVC_32", - "UK4_32", "UK5_32", "UK6_32", "ABT_32", - "UK8_32", "UK9_32", "UK10_32", "UND_32", - "UK12_32", "UK13_32", "UK14_32", "SYS_32", - }; - - flags = condition_codes (regs); - - printf ("pc : [<%08lx>] lr : [<%08lx>]\n" - "sp : %08lx ip : %08lx fp : %08lx\n", - instruction_pointer (regs), - regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); - printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", - regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); - printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", - regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); - printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", - regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); - printf ("Flags: %c%c%c%c", - flags & CC_N_BIT ? 'N' : 'n', - flags & CC_Z_BIT ? 'Z' : 'z', - flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); - printf (" IRQs %s FIQs %s Mode %s%s\n", - interrupts_enabled (regs) ? "on" : "off", - fast_interrupts_enabled (regs) ? "on" : "off", - processor_modes[processor_mode (regs)], - thumb_mode (regs) ? " (T)" : ""); -} - -void do_undefined_instruction (struct pt_regs *pt_regs) -{ - printf ("undefined instruction\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_software_interrupt (struct pt_regs *pt_regs) -{ - printf ("software interrupt\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_prefetch_abort (struct pt_regs *pt_regs) -{ - printf ("prefetch abort\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_data_abort (struct pt_regs *pt_regs) -{ - printf ("data abort\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_not_used (struct pt_regs *pt_regs) -{ - printf ("not used\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_fiq (struct pt_regs *pt_regs) -{ - printf ("fast interrupt request\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_irq (struct pt_regs *pt_regs) -{ - printf ("interrupt request\n"); - show_regs (pt_regs); - bad_mode (); -} - - -int interrupt_init (void) -{ - -/* we don't use interrupt */ - return(0); -} - -/* - * timer without interrupts - */ - -void reset_timer (void) -{ - reset_timer_masked (); -} - -ulong get_timer (ulong base) -{ - return get_timer_masked (); -} - -void set_timer (ulong t) -{ -/* Nop */ -} - -void udelay (unsigned long usec) -{ - udelay_masked (usec); -} - -void reset_timer_masked (void) -{ - u32 tmp; - MX1_TCTL1 = 0x09; - tmp = 0x1f; /* a little delay for timer to reset */ - MX1_TPRER1 = 0x1f; - MX1_TCTL1 = 0x19; -} - -ulong get_timer_masked (void) -{ - return MX1_TCN1; -} - -void udelay_masked (unsigned long usec) -{ - ulong tmo; - - tmo = usec / 1000; - tmo *= CFG_HZ; - tmo /= 1000; - - reset_timer_masked (); - - while (get_timer_masked () < tmo); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ - -ulong get_tbclk (void) { - return CFG_HZ; -} diff --git a/cpu/mc9328/serial.c b/cpu/mc9328/serial.c deleted file mode 100644 index 8dcfb80..0000000 --- a/cpu/mc9328/serial.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * cpu/mc9328/serial.c - * - * (c) Copyright 2004 - * Techware Information Technology, Inc. - * http://www.techware.com.tw/ - * - * Ming-Len Wu <minglen_wu@techware.com.tw> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <mc9328.h> - -#if defined(CONFIG_UART1) -/* GPIO PORT B */ - -#define reg_GIUS MX1_GIUS_C -#define reg_GPR MX1_GPR_B -#define GPIO_MASK 0xFFFFE1FF -#define UART_BASE 0x00206000 - -#elif defined (CONFIG_UART2) -/* GPIO PORT C */ - -#define reg_GIUS MX1_GIUS_C -#define reg_GPR MX1_GPR_C -#define GPIO_MASK 0x0FFFFFFF -#define UART_BASE 0x207000 - -#endif - -#define reg_URXD (*((volatile u32 *)(UART_BASE+0x00))) -#define reg_UTXD (*((volatile u32 *)(UART_BASE+0x40))) -#define reg_UCR1 (*((volatile u32 *)(UART_BASE+0x80))) -#define reg_UCR2 (*((volatile u32 *)(UART_BASE+0x84))) -#define reg_UCR3 (*((volatile u32 *)(UART_BASE+0x88))) -#define reg_UCR4 (*((volatile u32 *)(UART_BASE+0x8C))) -#define reg_UFCR (*((volatile u32 *)(UART_BASE+0x90))) -#define reg_USR1 (*((volatile u32 *)(UART_BASE+0x94))) -#define reg_USR2 (*((volatile u32 *)(UART_BASE+0x98))) -#define reg_UESC (*((volatile u32 *)(UART_BASE+0x9C))) -#define reg_UTIM (*((volatile u32 *)(UART_BASE+0xA0))) -#define reg_UBIR (*((volatile u32 *)(UART_BASE+0xA4))) -#define reg_UBMR (*((volatile u32 *)(UART_BASE+0xA8))) -#define reg_UBRC (*((volatile u32 *)(UART_BASE+0xAC))) - -#define TXFE_MASK 0x4000 /* Tx buffer empty */ -#define RDR_MASK 0x0001 /* receive data ready */ - -void serial_setbrg (void) { - - /* config I/O pins for UART */ - reg_GIUS &= GPIO_MASK; - reg_GPR &= GPIO_MASK; - - /* config UART */ - reg_UCR1 = 5; - reg_UCR2 = 0x4027; - reg_UCR4 = 1; - reg_UFCR = 0xA81; - - reg_UBIR = 0xF; - reg_UBMR = 0x8A; - reg_UBRC = 8; -} - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ - -int serial_init (void) { - serial_setbrg (); - - return (0); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int serial_getc (void) { - - while (!(reg_USR2 & RDR_MASK)) ; /* wait until RDR bit set */ - - return (u8)reg_URXD; -} - -/* - * Output a single byte to the serial port. - */ -void serial_putc (const char c) { - - while (!(reg_USR2 & TXFE_MASK)); /* wait until TXFE bit set */ - - reg_UTXD = (u16) c; - - if (c == '\n') { /* carriage return ? append line-feed */ - while (!(reg_USR2 & TXFE_MASK)); /* wait until TXFE bit set */ - reg_UTXD = '\r'; - } - -} - -/* - * Test whether a character is in the RX buffer - */ -int serial_tstc (void) { - return reg_USR2 & RDR_MASK; -} - -void serial_puts (const char *s) { - while (*s) { - serial_putc (*s++); - } -} diff --git a/cpu/mc9328/start.S b/cpu/mc9328/start.S deleted file mode 100644 index edfce12..0000000 --- a/cpu/mc9328/start.S +++ /dev/null @@ -1,388 +0,0 @@ -/* - * armboot - Startup Code for ARM920 CPU-core - * - * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> - * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> - * Copyright (c) 2002 Gary Jennejohn <gj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include <config.h> -#include <version.h> - - -/* - ************************************************************************* - * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq - - .balignl 16,0xdeadbeef - - -/* - ************************************************************************* - * - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * relocate armboot to ram - * setup stack - * jump to second stage - * - ************************************************************************* - */ - -_TEXT_BASE: - .word TEXT_BASE - -.globl _armboot_start -_armboot_start: - .word _start - -/* - * These are defined in the board-specific linker script. - */ -.globl _bss_start -_bss_start: - .word __bss_start - -.globl _bss_end -_bss_end: - .word _end - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - - -/* - * the actual reset code - */ - -reset: - /* - * set the cpu to SVC32 mode - */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 - - /* - * we do sys-critical inits only at reboot, - * not when booting from ram! - */ -#ifdef CONFIG_INIT_CRITICAL - bl cpu_init_crit -#endif - -relocate: /* relocate U-Boot to RAM */ - adr r0, _start /* r0 <- current position of code */ - ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ - cmp r0, r1 /* don't reloc during debug */ - beq stack_setup - - ldr r2, _armboot_start - ldr r3, _bss_start - sub r2, r3, r2 /* r2 <- size of armboot */ - add r2, r0, r2 /* r2 <- source end address */ - -copy_loop: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop - - /* Set up the stack */ -stack_setup: - ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ -#ifdef CONFIG_USE_IRQ - sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) -#endif - sub sp, r0, #12 /* leave 3 words for abort-stack */ - -clear_bss: - ldr r0, _bss_start /* find start of bss segment */ - ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ - -clbss_l:str r2, [r0] /* clear loop... */ - add r0, r0, #4 - cmp r0, r1 - bne clbss_l - - ldr pc, _start_armboot - -_start_armboot: .word start_armboot - - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ - - -cpu_init_crit: - /* - * flush v4 I/D caches - */ - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ - - /* - * disable MMU stuff and caches - */ - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) - bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) - orr r0, r0, #0x00000002 @ set bit 2 (A) Align - orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache - mcr p15, 0, r0, c1, c0, 0 - - - /* - * before relocating, we have to setup RAM timing - * because memory timing is board-dependend, you will - * find a memsetup.S in your board directory. - */ - mov ip, lr - bl memsetup - mov lr, ip - - mov pc, lr - - -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - ldr r2, _armboot_start - sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack - ldmia r2, {r2 - r3} @ get pc, cpsr - add r0, sp, #S_FRAME_SIZE @ restore sp_SVC - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, _armboot_start @ setup our mode stack - sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack - - str lr, [r13] @ save caller lr / spsr - mrs lr, spsr - str lr, [r13, #4] - - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 - mov lr, pc - movs pc, lr - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - - .align 5 -.globl reset_cpu -reset_cpu: - mov ip, #0 - mcr p15, 0, ip, c7, c7, 0 @ invalidate cache - mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4) - mrc p15, 0, ip, c1, c0, 0 @ get ctrl register - bic ip, ip, #0x000f @ ............wcam - bic ip, ip, #0x2100 @ ..v....s........ - mcr p15, 0, ip, c1, c0, 0 @ ctrl register - mov pc, r0 diff --git a/cpu/mpc824x/cpu_init.c b/cpu/mpc824x/cpu_init.c index 08f5c4a..d0c7a3b 100644 --- a/cpu/mpc824x/cpu_init.c +++ b/cpu/mpc824x/cpu_init.c @@ -108,7 +108,7 @@ cpu_init_f (void) CONFIG_READ_BYTE(PCMBCR,val); /* in order not to corrupt data which is being read over the PCI bus - * with the PPC as master, we need to reduce the number of PCMRBs to 1, + * with the PPC as slave, we need to reduce the number of PCMRBs to 1, * 4.11 in the processor user manual * */ @@ -117,6 +117,10 @@ cpu_init_f (void) #else CONFIG_WRITE_BYTE(PCMBCR,(val|0x80)); /* 2 PCMRBs */ CONFIG_WRITE_BYTE(PCMBCR,(val|0x40)); /* 3 PCMRBs */ + /* default, 4 PCMRBs are used, so don't change the + * register is this is _really_ what you want: data + * corruption with no performance gain + */ #endif #endif diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index d40cd8c..787f7fa 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -33,7 +33,6 @@ void get_sys_info (sys_info_t * sysInfo) { - DECLARE_GLOBAL_DATA_PTR; volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_gur_t *gur = &immap->im_gur; uint plat_ratio,e500_ratio; diff --git a/cpu/mpc8xx/scc.c b/cpu/mpc8xx/scc.c index 78b2f99..6b9110f 100644 --- a/cpu/mpc8xx/scc.c +++ b/cpu/mpc8xx/scc.c @@ -193,6 +193,10 @@ static int scc_init (struct eth_device *dev, bd_t * bis) volatile immap_t *immr = (immap_t *) CFG_IMMR; +#if defined(CONFIG_LWMON) + reset_phy(); +#endif + #ifdef CONFIG_FADS #if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC860T) /* The MPC86xADS/FADS860T don't use the MODEM_EN or DATA_VOICE signals. */ @@ -550,6 +554,8 @@ static void scc_halt (struct eth_device *dev) immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); + + immr->im_ioport.iop_pcso &= ~(PC_ENET_CLSN | PC_ENET_RENA); } #if 0 diff --git a/cpu/mpc8xx/serial.c b/cpu/mpc8xx/serial.c index 71f3ae1..fa0405f 100644 --- a/cpu/mpc8xx/serial.c +++ b/cpu/mpc8xx/serial.c @@ -24,49 +24,44 @@ #include <common.h> #include <commproc.h> #include <command.h> +#include <serial.h> #include <watchdog.h> #if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */ #if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */ #define SMC_INDEX 0 -#undef SCC_INDEX #define PROFF_SMC PROFF_SMC1 #define CPM_CR_CH_SMC CPM_CR_CH_SMC1 #elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */ #define SMC_INDEX 1 -#undef SCC_INDEX #define PROFF_SMC PROFF_SMC2 #define CPM_CR_CH_SMC CPM_CR_CH_SMC2 -#elif defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */ -#undef SMC_INDEX +#endif /* CONFIG_8xx_CONS_SMCx */ + +#if defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */ #define SCC_INDEX 0 #define PROFF_SCC PROFF_SCC1 #define CPM_CR_CH_SCC CPM_CR_CH_SCC1 #elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */ -#undef SMC_INDEX #define SCC_INDEX 1 #define PROFF_SCC PROFF_SCC2 #define CPM_CR_CH_SCC CPM_CR_CH_SCC2 #elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */ -#undef SMC_INDEX #define SCC_INDEX 2 #define PROFF_SCC PROFF_SCC3 #define CPM_CR_CH_SCC CPM_CR_CH_SCC3 #elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */ -#undef SMC_INDEX #define SCC_INDEX 3 #define PROFF_SCC PROFF_SCC4 #define CPM_CR_CH_SCC CPM_CR_CH_SCC4 -#else /* CONFIG_8xx_CONS_? */ -#error "console not correctly defined" -#endif +#endif /* CONFIG_8xx_CONS_SCCx */ static void serial_setdivisor(volatile cpm8xx_t *cp) { @@ -96,7 +91,23 @@ static void serial_setdivisor(volatile cpm8xx_t *cp) * as serial console interface. */ -int serial_init (void) +static void smc_setbrg (void) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile cpm8xx_t *cp = &(im->im_cpm); + + /* Set up the baud rate generator. + * See 8xx_io/commproc.c for details. + * + * Wire BRG1 to SMCx + */ + + cp->cp_simode = 0x00000000; + + serial_setdivisor(cp); +} + +static int smc_init (void) { volatile immap_t *im = (immap_t *)CFG_IMMR; volatile smc_t *sp; @@ -217,7 +228,7 @@ int serial_init (void) /* Set up the baud rate generator. */ - serial_setbrg (); + smc_setbrg (); /* Make the first buffer the only buffer. */ @@ -247,39 +258,8 @@ int serial_init (void) return (0); } -void -serial_setbrg (void) -{ - volatile immap_t *im = (immap_t *)CFG_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - - /* Set up the baud rate generator. - * See 8xx_io/commproc.c for details. - * - * Wire BRG1 to SMCx - */ - - cp->cp_simode = 0x00000000; - - serial_setdivisor(cp); -} - -#ifdef CONFIG_MODEM_SUPPORT -void disable_putc(void) -{ - DECLARE_GLOBAL_DATA_PTR; - gd->be_quiet = 1; -} - -void enable_putc(void) -{ - DECLARE_GLOBAL_DATA_PTR; - gd->be_quiet = 0; -} -#endif - -void -serial_putc(const char c) +static void +smc_putc(const char c) { volatile cbd_t *tbdf; volatile char *buf; @@ -295,7 +275,7 @@ serial_putc(const char c) #endif if (c == '\n') - serial_putc ('\r'); + smc_putc ('\r'); up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; @@ -317,8 +297,16 @@ serial_putc(const char c) } } -int -serial_getc(void) +static void +smc_puts (const char *s) +{ + while (*s) { + smc_putc (*s++); + } +} + +static int +smc_getc(void) { volatile cbd_t *rbdf; volatile unsigned char *buf; @@ -344,8 +332,8 @@ serial_getc(void) return(c); } -int -serial_tstc() +static int +smc_tstc(void) { volatile cbd_t *rbdf; volatile smc_uart_t *up; @@ -359,9 +347,41 @@ serial_tstc() return(!(rbdf->cbd_sc & BD_SC_EMPTY)); } -#else /* ! CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2 */ +struct serial_device serial_smc_device = +{ + "serial_smc", + "SMC", + smc_init, + smc_setbrg, + smc_getc, + smc_tstc, + smc_putc, + smc_puts, +}; + +#endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */ + +#if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \ + defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4) + +static void +scc_setbrg (void) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile cpm8xx_t *cp = &(im->im_cpm); -int serial_init (void) + /* Set up the baud rate generator. + * See 8xx_io/commproc.c for details. + * + * Wire BRG1 to SCCx + */ + + cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX)); + + serial_setdivisor(cp); +} + +static int scc_init (void) { volatile immap_t *im = (immap_t *)CFG_IMMR; volatile scc_t *sp; @@ -426,7 +446,7 @@ int serial_init (void) #ifdef CFG_ALLOC_DPRAM dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ; #else - dpaddr = CPM_SERIAL_BASE ; + dpaddr = CPM_SERIAL2_BASE ; #endif /* Enable SDMA. @@ -446,7 +466,7 @@ int serial_init (void) /* Set up the baud rate generator. */ - serial_setbrg (); + scc_setbrg (); /* Set up the uart parameters in the parameter ram. */ @@ -497,9 +517,11 @@ int serial_init (void) /* Set UART mode, clock divider 16 on Tx and Rx */ + sp->scc_gsmrl &= ~0xF; sp->scc_gsmrl |= (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16); + sp->scc_psmr = 0; sp->scc_psmr |= SCU_PSMR_CL; /* Mask all interrupts and remove anything pending. @@ -521,25 +543,8 @@ int serial_init (void) return (0); } -void -serial_setbrg (void) -{ - volatile immap_t *im = (immap_t *)CFG_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - - /* Set up the baud rate generator. - * See 8xx_io/commproc.c for details. - * - * Wire BRG1 to SCCx - */ - - cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX)); - - serial_setdivisor(cp); -} - -void -serial_putc(const char c) +static void +scc_putc(const char c) { volatile cbd_t *tbdf; volatile char *buf; @@ -547,8 +552,15 @@ serial_putc(const char c) volatile immap_t *im = (immap_t *)CFG_IMMR; volatile cpm8xx_t *cpmp = &(im->im_cpm); +#ifdef CONFIG_MODEM_SUPPORT + DECLARE_GLOBAL_DATA_PTR; + + if (gd->be_quiet) + return; +#endif + if (c == '\n') - serial_putc ('\r'); + scc_putc ('\r'); up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC]; @@ -570,8 +582,16 @@ serial_putc(const char c) } } -int -serial_getc(void) +static void +scc_puts (const char *s) +{ + while (*s) { + scc_putc (*s++); + } +} + +static int +scc_getc(void) { volatile cbd_t *rbdf; volatile unsigned char *buf; @@ -597,8 +617,8 @@ serial_getc(void) return(c); } -int -serial_tstc() +static int +scc_tstc(void) { volatile cbd_t *rbdf; volatile scc_uart_t *up; @@ -612,36 +632,66 @@ serial_tstc() return(!(rbdf->cbd_sc & BD_SC_EMPTY)); } -#endif /* CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2 */ - +struct serial_device serial_scc_device = +{ + "serial_scc", + "SCC", + scc_init, + scc_setbrg, + scc_getc, + scc_tstc, + scc_putc, + scc_puts, +}; + +#endif /* CONFIG_8xx_CONS_SCCx */ -void -serial_puts (const char *s) +#ifdef CONFIG_MODEM_SUPPORT +void disable_putc(void) { - while (*s) { - serial_putc (*s++); - } + DECLARE_GLOBAL_DATA_PTR; + gd->be_quiet = 1; } +void enable_putc(void) +{ + DECLARE_GLOBAL_DATA_PTR; + gd->be_quiet = 0; +} +#endif #if (CONFIG_COMMANDS & CFG_CMD_KGDB) void kgdb_serial_init(void) { + int i = -1; + + if (strcmp(default_serial_console()->ctlr, "SMC") == 0) + { #if defined(CONFIG_8xx_CONS_SMC1) - serial_printf("[on SMC1] "); + i = 1; #elif defined(CONFIG_8xx_CONS_SMC2) - serial_printf("[on SMC2] "); -#elif defined(CONFIG_8xx_CONS_SCC1) - serial_printf("[on SCC1] "); + i = 2; +#endif + } + else if (strcmp(default_serial_console()->ctlr, "SMC") == 0) + { +#if defined(CONFIG_8xx_CONS_SCC1) + i = 1; #elif defined(CONFIG_8xx_CONS_SCC2) - serial_printf("[on SCC2] "); + i = 2; #elif defined(CONFIG_8xx_CONS_SCC3) - serial_printf("[on SCC3] "); + i = 3; #elif defined(CONFIG_8xx_CONS_SCC4) - serial_printf("[on SCC4] "); + i = 4; #endif + } + + if (i >= 0) + { + serial_printf("[on %s%d] ", default_serial_console()->ctlr, i); + } } void diff --git a/cpu/mpc8xx/spi.c b/cpu/mpc8xx/spi.c index 5d75207..9213d10 100644 --- a/cpu/mpc8xx/spi.c +++ b/cpu/mpc8xx/spi.c @@ -39,7 +39,7 @@ #include <linux/ctype.h> #include <malloc.h> #include <post.h> -#include <net.h> +#include <serial.h> #if (defined(CONFIG_SPI)) || (CONFIG_POST & CFG_POST_SPI) @@ -542,13 +542,13 @@ int spi_post_test (int flags) cp->cp_spmode &= ~SPMODE_LOOP; /* - * SCC2 Ethernet parameter RAM space overlaps + * SCC2 parameter RAM space overlaps * the SPI parameter RAM space. So we need to restore - * the SCC2 configuration if it is used by UART or Ethernet. + * the SCC2 configuration if it is used by UART. */ -#if defined(CONFIG_8xx_CONS_SCC2) - serial_init (); +#if !defined(CONFIG_8xx_CONS_NONE) + serial_reinit_all (); #endif if (res != 0) { |