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author | Marian Balakowicz <m8@semihalf.com> | 2008-03-12 11:23:02 (GMT) |
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committer | Marian Balakowicz <m8@semihalf.com> | 2008-03-12 11:23:02 (GMT) |
commit | 7e492d8258182e31c988bbf9917d4a3d41949d56 (patch) | |
tree | e9c9db79d797cf487107c019537c6bb00b854c6c /cpu | |
parent | afe45c87e3c5d77bad76b1a57dccd20764d45b5d (diff) | |
parent | 30f1806f60978d707b0cff2d7bf89d141fc24290 (diff) | |
download | u-boot-7e492d8258182e31c988bbf9917d4a3d41949d56.tar.xz |
Merge branch 'master' of git://www.denx.de/git/u-boot into new-image
Diffstat (limited to 'cpu')
-rw-r--r-- | cpu/mpc512x/speed.c | 21 | ||||
-rw-r--r-- | cpu/mpc85xx/interrupts.c | 2 | ||||
-rw-r--r-- | cpu/mpc85xx/start.S | 18 | ||||
-rw-r--r-- | cpu/ppc4xx/4xx_enet.c | 15 | ||||
-rw-r--r-- | cpu/ppc4xx/miiphy.c | 5 |
5 files changed, 44 insertions, 17 deletions
diff --git a/cpu/mpc512x/speed.c b/cpu/mpc512x/speed.c index 99e3495..cfaffb5 100644 --- a/cpu/mpc512x/speed.c +++ b/cpu/mpc512x/speed.c @@ -67,12 +67,14 @@ int get_clocks (void) u8 cpmf; u8 sys_div; u8 ips_div; + u8 pci_div; u32 ref_clk = CFG_MPC512X_CLKIN; u32 spll; u32 sys_clk; u32 core_clk; u32 csb_clk; u32 ips_clk; + u32 pci_clk; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) return -1; @@ -95,8 +97,16 @@ int get_clocks (void) /* in case we cannot get a sane IPS divisor, fail gracefully */ ips_clk = 0; } + pci_div = (im->clk.scfr[0] & SCFR1_PCI_DIV_MASK) >> SCFR1_PCI_DIV_SHIFT; + if (pci_div != 0) { + pci_clk = csb_clk / pci_div; + } else { + /* in case we cannot get a sane IPS divisor, fail gracefully */ + pci_clk = 333333; + } gd->ips_clk = ips_clk; + gd->pci_clk = pci_clk; gd->csb_clk = csb_clk; gd->cpu_clk = core_clk; gd->bus_clk = csb_clk; @@ -115,11 +125,12 @@ ulong get_bus_freq (ulong dummy) int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - printf ("Clock configuration:\n"); - printf (" CPU: %4d MHz\n", gd->cpu_clk / 1000000); - printf (" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000); - printf (" IPS Bus: %4d MHz\n", gd->ips_clk / 1000000); - printf (" DDR: %4d MHz\n", 2 * gd->csb_clk / 1000000); + printf("Clock configuration:\n"); + printf(" CPU: %4d MHz\n", gd->cpu_clk / 1000000); + printf(" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000); + printf(" IPS Bus: %4d MHz\n", gd->ips_clk / 1000000); + printf(" PCI: %4d MHz\n", gd->pci_clk / 1000000); + printf(" DDR: %4d MHz\n", 2 * gd->csb_clk / 1000000); return 0; } diff --git a/cpu/mpc85xx/interrupts.c b/cpu/mpc85xx/interrupts.c index 18e5377..4fe1fac 100644 --- a/cpu/mpc85xx/interrupts.c +++ b/cpu/mpc85xx/interrupts.c @@ -91,7 +91,7 @@ int interrupt_init (void) set_msr (get_msr () | MSR_EE); #ifdef CONFIG_INTERRUPTS - pic->iivpr1 = 0x810002; /* 50220 enable ecm interrupts */ + pic->iivpr1 = 0x810001; /* 50220 enable ecm interrupts */ debug("iivpr1@%x = %x\n",&pic->iivpr1, pic->iivpr1); pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */ diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index eb24dbc..15b804d 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -992,7 +992,6 @@ trap_reloc: blr -#ifdef CFG_INIT_RAM_LOCK .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ @@ -1002,11 +1001,20 @@ unlock_ram_in_cache: andi. r4,r4,0x1ff slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) mtctr r4 -1: icbi r0,r3 - dcbi r0,r3 +1: dcbi r0,r3 addi r3,r3,CFG_CACHELINE_SIZE bdnz 1b - sync /* Wait for all icbi to complete on bus */ + sync + + /* Invalidate the TLB entries for the cache */ + lis r3,CFG_INIT_RAM_ADDR@h + ori r3,r3,CFG_INIT_RAM_ADDR@l + tlbivax 0,r3 + addi r3,r3,0x1000 + tlbivax 0,r3 + addi r3,r3,0x1000 + tlbivax 0,r3 + addi r3,r3,0x1000 + tlbivax 0,r3 isync blr -#endif diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 44659ff..599f5ce 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -487,6 +487,9 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #endif u32 bd_cached; u32 bd_uncached = 0; +#ifdef CONFIG_4xx_DCACHE + static u32 last_used_ea = 0; +#endif EMAC_4XX_HW_PST hw_p = dev->priv; @@ -850,7 +853,12 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #ifdef CONFIG_4xx_DCACHE flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE); - bd_uncached = bis->bi_memsize; + if (!last_used_ea) + bd_uncached = bis->bi_memsize; + else + bd_uncached = last_used_ea + MAL_ALLOC_SIZE; + + last_used_ea = bd_uncached; program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE, TLB_WORD2_I_ENABLE); #else @@ -967,9 +975,10 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) /* set transmit enable & receive enable */ out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); - /* set receive fifo to 4k and tx fifo to 2k */ mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr); - mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K; + + /* set rx-/tx-fifo size */ + mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE; /* set speed */ if (speed == _1000BASET) { diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c index 4216f0b..3978773 100644 --- a/cpu/ppc4xx/miiphy.c +++ b/cpu/ppc4xx/miiphy.c @@ -143,9 +143,8 @@ int phy_setup_aneg (char *devname, unsigned char addr) u16 adv; miiphy_read (devname, addr, PHY_ANAR, &adv); - adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 | - PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD | - PHY_ANLPAR_10); + adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | + PHY_ANLPAR_10FD | PHY_ANLPAR_10); miiphy_write (devname, addr, PHY_ANAR, adv); miiphy_read (devname, addr, PHY_1000BTCR, &adv); |