diff options
author | wdenk <wdenk> | 2004-08-01 23:02:45 (GMT) |
---|---|---|
committer | wdenk <wdenk> | 2004-08-01 23:02:45 (GMT) |
commit | 9aea95307fdb0ffe0d3a98a17ac73e5040c9756a (patch) | |
tree | 812e59d74bb6ab942f7c797b6bbcc5e7c2ad4a8f /cpu | |
parent | 281e00a3be453a169d854f824a460359d10f92bb (diff) | |
download | u-boot-9aea95307fdb0ffe0d3a98a17ac73e5040c9756a.tar.xz |
Patch by Jon Loeliger, 16 Jul 2004:
- support larger DDR memories up to 2G on the PC8540/8560ADS and
STXGP3 boards
- Made MPC8540/8560ADS be 33Mhz PCI by default.
- Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
and CONFIG_L2_INIT_RAM options.
- Refactor Local Bus initialization out of SDRAM setup.
- Re-implement new version of LBC11/DDR11 errata workarounds.
- Moved board specific PCI init parts out of CPU directory.
- Added TLB entry for PCI-1 IO Memory
- Updated README.mpc85xxads
Diffstat (limited to 'cpu')
-rw-r--r-- | cpu/mpc85xx/pci.c | 78 | ||||
-rw-r--r-- | cpu/mpc85xx/spd_sdram.c | 402 | ||||
-rw-r--r-- | cpu/mpc85xx/start.S | 36 | ||||
-rw-r--r-- | cpu/mpc85xx/traps.c | 10 |
4 files changed, 314 insertions, 212 deletions
diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index 11f0c3e..60c1e61 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -32,34 +32,10 @@ #if defined(CONFIG_PCI) - -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc85xxads_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, - {} -}; -#endif - -struct pci_controller local_hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_mpc85xxads_config_table, -#endif -}; - - -void pci_init_board (void) +void +pci_mpc85xx_init(struct pci_controller *hose) { - struct pci_controller *hose = (struct pci_controller *) &local_hose; - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile immap_t *immap = (immap_t *)CFG_CCSRBAR; volatile ccsr_pcix_t *pcix = &immap->im_pcix; u16 reg16; @@ -67,39 +43,45 @@ void pci_init_board (void) hose->first_busno = 0; hose->last_busno = 0xff; - pci_set_region (hose->regions + 0, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_SIZE, PCI_REGION_MEM); + pci_set_region(hose->regions + 0, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); - pci_set_region (hose->regions + 1, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO); + pci_set_region(hose->regions + 1, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); hose->region_count = 2; - pci_setup_indirect (hose, (CFG_IMMR + 0x8000), (CFG_IMMR + 0x8004)); + pci_setup_indirect(hose, + (CFG_IMMR+0x8000), + (CFG_IMMR+0x8004)); - pci_read_config_word (PCI_BDF (0, 0, 0), PCI_COMMAND, ®16); + pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config_word (PCI_BDF (0, 0, 0), PCI_COMMAND, reg16); + pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16); /* * Clear non-reserved bits in status register. */ - pci_write_config_word (PCI_BDF (0, 0, 0), PCI_STATUS, 0xffff); - pci_write_config_byte (PCI_BDF (0, 0, 0), PCI_LATENCY_TIMER, 0x80); + pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); + pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80); - pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; - pcix->potear1 = 0x00000000; - pcix->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; + pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; + pcix->potear1 = 0x00000000; + pcix->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; pcix->powbear1 = 0x00000000; - pcix->powar1 = 0x8004401c; /* 512M MEM space */ + pcix->powar1 = 0x8004401c; /* 512M MEM space */ - pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; - pcix->potear2 = 0x00000000; - pcix->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; + pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; + pcix->potear2 = 0x00000000; + pcix->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; pcix->powbear2 = 0x00000000; - pcix->powar2 = 0x80088017; /* 16M IO space */ + pcix->powar2 = 0x80088017; /* 16M IO space */ pcix->pitar1 = 0x00000000; pcix->piwbar1 = 0x00000000; @@ -108,8 +90,8 @@ void pci_init_board (void) /* * Hose scan. */ - pci_register_hose (hose); - hose->last_busno = pci_hose_scan (hose); + pci_register_hose(hose); + hose->last_busno = pci_hose_scan(hose); } #endif /* CONFIG_PCI */ diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 02b29ad..3d7d003 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -30,133 +30,171 @@ #ifdef CONFIG_SPD_EEPROM -#define ns2clk(ns) ((ns) / (2000000000 /get_bus_freq(0) + 1) + 1) -long int spd_sdram(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr = &immap->im_ddr; +#if defined(CONFIG_DDR_ECC) +extern void dma_init(void); +extern uint dma_check(void); +extern int dma_xfer(void *dest, uint count, void *src); +#endif + + +#ifndef CFG_READ_SPD +#define CFG_READ_SPD i2c_read +#endif + + +/* + * Convert picoseconds into clock cycles (rounding up if needed). + */ + +int +picos_to_clk(int picos) +{ + int clks; + + clks = picos / (2000000000 / (get_bus_freq(0) / 1000)); + if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) { + clks++; + } + + return clks; +} + + +unsigned int +banksize(unsigned char row_dens) +{ + return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24; +} + + +long int +spd_sdram(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr = &immap->im_ddr; volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm; - spd_eeprom_t spd; - unsigned int memsize,tmp,tmp1,tmp2; + spd_eeprom_t spd; + unsigned tmp, tmp1; + unsigned int memsize; + unsigned int tlb_size; + unsigned int law_size; unsigned char caslat; + unsigned int ram_tlb_index; + unsigned int ram_tlb_address; - i2c_read (SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd)); + CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd)); - if ( spd.nrows > 2 ) { - printf("DDR:Only two chip selects are supported on ADS.\n"); + if (spd.nrows > 2) { + puts("DDR:Only two chip selects are supported on ADS.\n"); return 0; } - if ( spd.nrow_addr < 12 || spd.nrow_addr > 14 || spd.ncol_addr < 8 || spd.ncol_addr > 11) { - printf("DDR:Row or Col number unsupported.\n"); + if (spd.nrow_addr < 12 + || spd.nrow_addr > 14 + || spd.ncol_addr < 8 + || spd.ncol_addr > 11) { + puts("DDR:Row or Col number unsupported.\n"); return 0; } - ddr->cs0_bnds = ((spd.row_dens>>2) - 1); - ddr->cs0_config = ( 1<<31 | (spd.nrow_addr-12)<<8 | (spd.ncol_addr-8) ); - debug ("\n"); - debug ("cs0_bnds = 0x%08x\n",ddr->cs0_bnds); - debug ("cs0_config = 0x%08x\n",ddr->cs0_config); - if ( spd.nrows == 2 ) { - ddr->cs1_bnds = ((spd.row_dens<<14) | ((spd.row_dens>>1) - 1)); - ddr->cs1_config = ( 1<<31 | (spd.nrow_addr-12)<<8 | (spd.ncol_addr-8) ); - debug ("cs1_bnds = 0x%08x\n",ddr->cs1_bnds); - debug ("cs1_config = 0x%08x\n",ddr->cs1_config); + ddr->cs0_bnds = (banksize(spd.row_dens) >> 24) - 1; + ddr->cs0_config = ( 1 << 31 + | (spd.nrow_addr - 12) << 8 + | (spd.ncol_addr - 8) ); + debug("\n"); + debug("cs0_bnds = 0x%08x\n",ddr->cs0_bnds); + debug("cs0_config = 0x%08x\n",ddr->cs0_config); + + if (spd.nrows == 2) { + ddr->cs1_bnds = ( (banksize(spd.row_dens) >> 8) + | ((banksize(spd.row_dens) >> 23) - 1) ); + ddr->cs1_config = ( 1<<31 + | (spd.nrow_addr-12) << 8 + | (spd.ncol_addr-8) ); + debug("cs1_bnds = 0x%08x\n",ddr->cs1_bnds); + debug("cs1_config = 0x%08x\n",ddr->cs1_config); } - memsize = spd.nrows * (4 * spd.row_dens); - if( spd.mem_type != 0x07 ) { - printf("No DDR module found!\n"); + if (spd.mem_type != 0x07) { + puts("No DDR module found!\n"); return 0; } + /* + * Figure out memory size in Megabytes. + */ + memsize = spd.nrows * banksize(spd.row_dens) / 0x100000; + + /* + * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord. + */ + law_size = 19 + __ilog2(memsize); + + /* + * Determine size of each TLB1 entry. + */ switch (memsize) { case 16: - tmp = 7; /* TLB size */ - tmp1 = 1; /* TLB entry number */ - tmp2 = 23; /* Local Access Window size */ - break; case 32: - tmp = 7; - tmp1 = 2; - tmp2 = 24; + tlb_size = BOOKE_PAGESZ_16M; break; case 64: - tmp = 8; - tmp1 = 1; - tmp2 = 25; - break; case 128: - tmp = 8; - tmp1 = 2; - tmp2 = 26; + tlb_size = BOOKE_PAGESZ_64M; break; case 256: - tmp = 9; - tmp1 = 1; - tmp2 = 27; - break; case 512: - tmp = 9; - tmp1 = 2; - tmp2 = 28; - break; case 1024: - tmp = 10; - tmp1 = 1; - tmp2 = 29; + case 2048: + tlb_size = BOOKE_PAGESZ_256M; break; default: - printf ("DDR:we only added support 16M,32M,64M,128M,256M,512M and 1G DDR I.\n"); + puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G DDR I are supported.\n"); return 0; break; } - /* configure DDR TLB to TLB1 Entry 4,5 */ - mtspr(MAS0, TLB1_MAS0(1,4,0)); - mtspr(MAS1, TLB1_MAS1(1,1,0,0,tmp)); - mtspr(MAS2, TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)); - mtspr(MAS3, TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)); - asm volatile("isync;msync;tlbwe;isync"); - debug ("DDR:MAS0=0x%08x\n",TLB1_MAS0(1,4,0)); - debug ("DDR:MAS1=0x%08x\n",TLB1_MAS1(1,1,0,0,tmp)); - debug ("DDR:MAS2=0x%08x\n",TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) \ - & 0xfffff),0,0,0,0,0,0,0,0)); - debug ("DDR:MAS3=0x%08x\n",TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) \ - & 0xfffff),0,0,0,0,0,1,0,1,0,1)); - - if(tmp1 == 2) { - mtspr(MAS0, TLB1_MAS0(1,5,0)); - mtspr(MAS1, TLB1_MAS1(1,1,0,0,tmp)); - mtspr(MAS2, TLB1_MAS2((((CFG_DDR_SDRAM_BASE+(memsize*1024*1024)/2)>>12) \ - & 0xfffff),0,0,0,0,0,0,0,0)); - mtspr(MAS3, TLB1_MAS3((((CFG_DDR_SDRAM_BASE+(memsize*1024*1024)/2)>>12) \ - & 0xfffff),0,0,0,0,0,1,0,1,0,1)); + /* + * Configure DDR TLB1 entries. + * Starting at TLB1 8, use no more than 8 TLB1 entries. + */ + ram_tlb_index = 8; + ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE; + while (ram_tlb_address < (memsize * 1024 * 1024) + && ram_tlb_index < 16) { + mtspr(MAS0, TLB1_MAS0(1, ram_tlb_index, 0)); + mtspr(MAS1, TLB1_MAS1(1, 1, 0, 0, tlb_size)); + mtspr(MAS2, TLB1_MAS2(E500_TLB_EPN(ram_tlb_address), + 0, 0, 0, 0, 0, 0, 0, 0)); + mtspr(MAS3, TLB1_MAS3(E500_TLB_RPN(ram_tlb_address), + 0, 0, 0, 0, 0, 1, 0, 1, 0, 1)); asm volatile("isync;msync;tlbwe;isync"); - debug ("DDR:MAS0=0x%08x\n",TLB1_MAS0(1,5,0)); - debug ("DDR:MAS1=0x%08x\n",TLB1_MAS1(1,1,0,0,tmp)); - debug ("DDR:MAS2=0x%08x\n",TLB1_MAS2((((CFG_DDR_SDRAM_BASE \ - +(memsize*1024*1024)/2)>>12) & 0xfffff),0,0,0,0,0,0,0,0)); - debug ("DDR:MAS3=0x%08x\n",TLB1_MAS3((((CFG_DDR_SDRAM_BASE \ - +(memsize*1024*1024)/2)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)); + + debug("DDR:MAS0=0x%08x\n", TLB1_MAS0(1, ram_tlb_index, 0)); + debug("DDR:MAS1=0x%08x\n", TLB1_MAS1(1, 1, 0, 0, tlb_size)); + debug("DDR:MAS2=0x%08x\n", + TLB1_MAS2(E500_TLB_EPN(ram_tlb_address), + 0, 0, 0, 0, 0, 0, 0, 0)); + debug("DDR:MAS3=0x%08x\n", + TLB1_MAS3(E500_TLB_RPN(ram_tlb_address), + 0, 0, 0, 0, 0, 1, 0, 1, 0, 1)); + + ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2)); + ram_tlb_index++; } -#if defined(CONFIG_RAM_AS_FLASH) - ecm->lawbar2 = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff); - ecm->lawar2 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & tmp2)); - debug ("DDR:LAWBAR2=0x%08x\n",ecm->lawbar2); - debug ("DDR:LARAR2=0x%08x\n",ecm->lawar2); -#else + /* + * Set up LAWBAR for all of DDR. + */ ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff); - ecm->lawar1 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & tmp2)); - debug ("DDR:LAWBAR1=0x%08x\n",ecm->lawbar1); - debug ("DDR:LARAR1=0x%08x\n",ecm->lawar1); -#endif - - tmp = 20000/(((spd.clk_cycle & 0xF0) >> 4) * 10 + (spd.clk_cycle & 0x0f)); - debug ("DDR:Module maximum data rate is: %dMhz\n",tmp); + ecm->lawar1 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size)); + debug("DDR:LAWBAR1=0x%08x\n", ecm->lawbar1); + debug("DDR:LARAR1=0x%08x\n", ecm->lawar1); - /* find the largest CAS */ + /* + * find the largest CAS + */ if(spd.cas_lat & 0x40) { caslat = 7; } else if (spd.cas_lat & 0x20) { @@ -172,46 +210,65 @@ long int spd_sdram(void) { } else if (spd.cas_lat & 0x01) { caslat = 1; } else { - printf("DDR:no valid CAS Latency information.\n"); + puts("DDR:no valid CAS Latency information.\n"); return 0; } - tmp1 = get_bus_freq(0)/1000000; - if(tmp1<230 && tmp1>=90 && tmp>=230) { + tmp = 20000 / (((spd.clk_cycle & 0xF0) >> 4) * 10 + + (spd.clk_cycle & 0x0f)); + debug("DDR:Module maximum data rate is: %dMhz\n", tmp); + + tmp1 = get_bus_freq(0) / 1000000; + if (tmp1 < 230 && tmp1 >= 90 && tmp >= 230) { /* 90~230 range, treated as DDR 200 */ - if(spd.clk_cycle3 == 0xa0) caslat -= 2; - else if(spd.clk_cycle2 == 0xa0) caslat--; - } else if(tmp1<280 && tmp1>=230 && tmp>=280) { + if (spd.clk_cycle3 == 0xa0) + caslat -= 2; + else if(spd.clk_cycle2 == 0xa0) + caslat--; + } else if (tmp1 < 280 && tmp1 >= 230 && tmp >= 280) { /* 230-280 range, treated as DDR 266 */ - if(spd.clk_cycle3 == 0x75) caslat -= 2; - else if(spd.clk_cycle2 == 0x75) caslat--; - } else if(tmp1<350 && tmp1>=280 && tmp>=350) { + if (spd.clk_cycle3 == 0x75) + caslat -= 2; + else if (spd.clk_cycle2 == 0x75) + caslat--; + } else if (tmp1 < 350 && tmp1 >= 280 && tmp >= 350) { /* 280~350 range, treated as DDR 333 */ - if(spd.clk_cycle3 == 0x60) caslat -= 2; - else if(spd.clk_cycle2 == 0x60) caslat--; - } else if(tmp1<90 || tmp1 >=350) { /* DDR rate out-of-range */ - printf("DDR:platform frequency is not fit for DDR rate\n"); + if (spd.clk_cycle3 == 0x60) + caslat -= 2; + else if (spd.clk_cycle2 == 0x60) + caslat--; + } else if (tmp1 < 90 || tmp1 >= 350) { + /* DDR rate out-of-range */ + puts("DDR:platform frequency is not fit for DDR rate\n"); return 0; } - /* note: caslat must also be programmed into ddr->sdram_mode - register */ - /* note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,use - conservative value here */ - ddr->timing_cfg_1 = (((ns2clk(spd.trp/4) & 0x07) << 28 ) | \ - ((ns2clk(spd.tras) & 0x0f ) << 24 ) | \ - ((ns2clk(spd.trcd/4) & 0x07) << 20 ) | \ - ((caslat & 0x07)<< 16 ) | \ - (((ns2clk(spd.sset[6]) - 8) & 0x0f) << 12 ) | \ - ( 0x300 ) | \ - ((ns2clk(spd.trrd/4) & 0x07) << 4) | 1); - - debug ("DDR:timing_cfg_1=0x%08x\n",ddr->timing_cfg_1); + /* + * note: caslat must also be programmed into ddr->sdram_mode + * register. + * + * note: WRREC(Twr) and WRTORD(Twtr) are not in SPD, + * use conservative value here. + */ + ddr->timing_cfg_1 = + (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | + ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | + ((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) | + ((caslat & 0x07) << 16 ) | + (((picos_to_clk(spd.sset[6] * 1000) - 8) & 0x0f) << 12 ) | + ( 0x300 ) | + ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1); ddr->timing_cfg_2 = 0x00000800; - debug ("DDR:timing_cfg_2=0x%08x\n",ddr->timing_cfg_2); - /* only DDR I is supported, DDR I and II have different mode-register-set definition */ + debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1); + debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2); + + /* + * Only DDR I is supported + * DDR I and II have different mode-register-set definition + */ + /* burst length is always 4 */ switch(caslat) { case 2: @@ -227,53 +284,58 @@ long int spd_sdram(void) { ddr->sdram_mode = 0x32; /* 3.0 */ break; default: - printf("DDR:only CAS Latency 1.5,2.0,2.5,3.0 is supported.\n"); + puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n"); return 0; } - debug ("DDR:sdram_mode=0x%08x\n",ddr->sdram_mode); + debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode); switch(spd.refresh) { case 0x00: case 0x80: - tmp = ns2clk(15625); + tmp = picos_to_clk(15625000); break; case 0x01: case 0x81: - tmp = ns2clk(3900); + tmp = picos_to_clk(3900000); break; case 0x02: case 0x82: - tmp = ns2clk(7800); + tmp = picos_to_clk(7800000); break; case 0x03: case 0x83: - tmp = ns2clk(31300); + tmp = picos_to_clk(31300000); break; case 0x04: case 0x84: - tmp = ns2clk(62500); + tmp = picos_to_clk(62500000); break; case 0x05: case 0x85: - tmp = ns2clk(125000); + tmp = picos_to_clk(125000000); break; default: tmp = 0x512; break; } - /* set BSTOPRE to 0x100 for page mode, if auto-charge is used, set BSTOPRE = 0 */ + /* + * Set BSTOPRE to 0x100 for page mode + * If auto-charge is used, set BSTOPRE = 0 + */ ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100; - debug ("DDR:sdram_interval=0x%08x\n",ddr->sdram_interval); + debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval); - /* is this an ECC DDR chip? */ + /* + * Is this an ECC DDR chip? + */ #if defined(CONFIG_DDR_ECC) - if(spd.config == 0x02) { + if (spd.config == 0x02) { ddr->err_disable = 0x0000000d; ddr->err_sbe = 0x00ff0000; } - debug ("DDR:err_disable=0x%08x\n",ddr->err_disable); - debug ("DDR:err_sbe=0x%08x\n",ddr->err_sbe); + debug("DDR:err_disable=0x%08x\n", ddr->err_disable); + debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe); #endif asm("sync;isync;msync"); @@ -287,7 +349,8 @@ long int spd_sdram(void) { ddr->sdram_clk_cntl = 0x83000000; #endif - /* Figure out the settings for the sdram_cfg register. Build up + /* + * Figure out the settings for the sdram_cfg register. Build up * the entire register in 'tmp' before writing since the write into * the register will actually enable the memory controller, and all * settings must be done before enabling. @@ -298,7 +361,8 @@ long int spd_sdram(void) { */ tmp = 0xc2000000; - /* sdram_cfg[3] = RD_EN - registered DIMM enable + /* + * sdram_cfg[3] = RD_EN - registered DIMM enable * A value of 0x26 indicates micron registered DIMMS (micron.com) */ if (spd.mod_attr == 0x26) { @@ -306,13 +370,14 @@ long int spd_sdram(void) { } #if defined(CONFIG_DDR_ECC) - /* If the user wanted ECC (enabled via sdram_cfg[2]) */ + /* + * If the user wanted ECC (enabled via sdram_cfg[2]) + */ if (spd.config == 0x02) { tmp |= 0x20000000; } #endif - /* * REV1 uses 1T timing. * REV2 may use 1T or 2T as configured by the user. @@ -333,12 +398,71 @@ long int spd_sdram(void) { ddr->sdram_cfg = tmp; asm("sync;isync;msync"); - udelay(500); - debug ("DDR:sdram_cfg=0x%08x\n",ddr->sdram_cfg); + debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg); - return (memsize*1024*1024); + return memsize * 1024 * 1024; } #endif /* CONFIG_SPD_EEPROM */ + + +#if defined(CONFIG_DDR_ECC) +/* + * Initialize all of memory for ECC, then enable errors. + */ + +void +ddr_enable_ecc(unsigned int dram_size) +{ + uint *p = 0; + uint i = 0; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr; + + dma_init(); + + for (*p = 0; p < (uint *)(8 * 1024); p++) { + if (((unsigned int)p & 0x1f) == 0) { + ppcDcbz((unsigned long) p); + } + *p = (unsigned int)0xdeadbeef; + if (((unsigned int)p & 0x1c) == 0x1c) { + ppcDcbf((unsigned long) p); + } + } + + /* 8K */ + dma_xfer((uint *)0x2000, 0x2000, (uint *)0); + /* 16K */ + dma_xfer((uint *)0x4000, 0x4000, (uint *)0); + /* 32K */ + dma_xfer((uint *)0x8000, 0x8000, (uint *)0); + /* 64K */ + dma_xfer((uint *)0x10000, 0x10000, (uint *)0); + /* 128k */ + dma_xfer((uint *)0x20000, 0x20000, (uint *)0); + /* 256k */ + dma_xfer((uint *)0x40000, 0x40000, (uint *)0); + /* 512k */ + dma_xfer((uint *)0x80000, 0x80000, (uint *)0); + /* 1M */ + dma_xfer((uint *)0x100000, 0x100000, (uint *)0); + /* 2M */ + dma_xfer((uint *)0x200000, 0x200000, (uint *)0); + /* 4M */ + dma_xfer((uint *)0x400000, 0x400000, (uint *)0); + + for (i = 1; i < dram_size / 0x800000; i++) { + dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0); + } + + /* + * Enable errors for ECC. + */ + ddr->err_disable = 0x00000000; + asm("sync;isync;msync"); +} + +#endif /* CONFIG_DDR_ECC */ diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 885f1ab..9207396 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -218,7 +218,19 @@ _start_e500: mtspr MMUCSR0, r2 isync - /* After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e. + /* + * Invalidate all TLB0 entries. + */ + li r3,4 + li r4,0 + tlbivax r4,r3 + /* + * To avoid REV1 Errata CPU6 issues, make sure + * the instruction following tlbivax is not a store. + */ + + /* + * After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e. * 0xff700000-0xff800000. We need add a TLB1 entry for this 1MB * region before we can access any CCSR registers such as L2 * registers, Local Access Registers,etc. We will also re-allocate @@ -230,7 +242,7 @@ _start_e500: */ bl tlb1_entry mr r5,r0 - li r1,0x000f /* max 16 TLB1 entries */ + li r1,0x0020 /* max 16 TLB1 plus some TLB0 entries */ mtctr r1 lwzu r4,0(r5) /* how many TLB1 entries we actually use */ @@ -273,15 +285,6 @@ _start_e500: isync #endif - /* invalidate all TLB0 entries */ - li r3,4 - li r4,0 - tlbivax r4,r3 - /* - * To avoid REV1 Errata CPU6 issues, make sure - * the instruction following tlbivax is not a store. - */ - /* set up local access windows, defined at board/<boardname>/init.S */ lis r7,CFG_CCSRBAR@h @@ -289,21 +292,12 @@ _start_e500: bl law_entry mr r6,r0 -#if defined(CONFIG_RAM_AS_FLASH) - li r1,0x0006 -#else - li r1,0x0007 /*we have 8 LAWs, but reseve one for boot-over-rio-or-pci */ -#endif + li r1,0x0007 /* 8 LAWs, but reserve one for boot-over-rio-or-pci */ mtctr r1 lwzu r5,0(r6) /* how many windows we actually use */ -#if defined(CONFIG_RAM_AS_FLASH) - li r2,0x0c48 - li r1,0x0c50 -#else li r2,0x0c28 /* the first pair is reserved for boot-over-rio-or-pci */ li r1,0x0c30 -#endif 0: cmpwi r5,0 beq 1f diff --git a/cpu/mpc85xx/traps.c b/cpu/mpc85xx/traps.c index a348eab..a87eed2 100644 --- a/cpu/mpc85xx/traps.c +++ b/cpu/mpc85xx/traps.c @@ -22,7 +22,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -46,9 +46,10 @@ int (*debugger_exception_handler)(struct pt_regs *) = 0; /* Returns 0 if exception not found and fixup otherwise. */ extern unsigned long search_exception_table(unsigned long); -/* THIS NEEDS CHANGING to use the board info structure. +/* + * End of memory as shown by board info and determined by DDR setup. */ -#define END_OF_MEM (CFG_SDRAM_SIZE * 1024 * 1024) +#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize) static __inline__ void set_tsr(unsigned long val) @@ -82,6 +83,7 @@ extern void do_bedbug_breakpoint(struct pt_regs *); void print_backtrace(unsigned long *sp) { + DECLARE_GLOBAL_DATA_PTR; int cnt = 0; unsigned long i; @@ -261,7 +263,7 @@ DebugException(struct pt_regs *regs) #endif } -/* Probe an address by reading. If not present, return -1, otherwise +/* Probe an address by reading. If not present, return -1, otherwise * return 0. */ int |