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| author | Jon Loeliger <jdl@freescale.com> | 2006-06-16 02:56:28 (GMT) |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2006-06-16 02:56:28 (GMT) |
| commit | bee01a3c166bc7ef4903e4e756d58a109067283f (patch) | |
| tree | 9afb46e306367b9d0ce80ea7a818caad76ee85bf /cpu | |
| parent | 8bb683b6278e44d65c8a15ad9741497d5f445354 (diff) | |
| parent | 0e4c2a17ca34001ed36d259f13cb88ada4611a8c (diff) | |
| download | u-boot-bee01a3c166bc7ef4903e4e756d58a109067283f.tar.xz | |
Merge branch 'mpc86xx'
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/mpc86xx/start.S | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 07e7557..12bf75b 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -1196,13 +1196,6 @@ secondary_cpu_setup: sync #endif - /* setup the bats */ - bl setup_bats - sync - /* enable address translation */ - bl enable_addr_trans - sync - /* enable and invalidate the data cache */ bl dcache_enable sync @@ -1211,14 +1204,6 @@ secondary_cpu_setup: bl icache_enable sync - /* Set up MSR and HID0, HID1*/ - /* Enable interrupts */ -/* mfmsr r28 - li r4,0 - ori r4,r4,MSR_EE - or r28,r28,r4 - mtmsr r28 - */ /* TBEN in HID0 */ mfspr r4, HID0 |