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authorYork Sun <yorksun@freescale.com>2011-01-10 12:03:00 (GMT)
committerKumar Gala <galak@kernel.crashing.org>2011-01-20 04:58:23 (GMT)
commite1fd16b6f5e80d932c73f5a36141adfb35126e83 (patch)
tree7a1bda7894afa9187f50936172aff0529324d7b1 /doc/README.LED
parentd2a9568c57f0aa02f097911d3811e002a1eec1b8 (diff)
downloadu-boot-e1fd16b6f5e80d932c73f5a36141adfb35126e83.tar.xz
mpc85xx: Enable unique mode registers and dynamic ODT for DDR3
Added fsl_ddr_get_version() function to for DDR3 to poll DDRC IP version (major, minor, errata) to determine if unique mode registers are available. If true, always use unique mode registers. Dynamic ODT is enabled if needed. The table is documented in doc/README.fsl-ddr. This function may also need to be extend for future other platforms if such a feature exists. Enable address parity and RCW by default for RDIMMs. Change default output driver impedance from 34 ohm to 40ohm. Make it 34ohm for quad-rank RDIMMs. Use a formula to calculate rodt_on for timing_cfg_5. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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