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author | Stefan Roese <sr@denx.de> | 2016-04-21 06:19:42 (GMT) |
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committer | Heiko Schocher <hs@denx.de> | 2016-04-25 05:31:58 (GMT) |
commit | ba5da550ae1d955e53691e51cd74a27331ca3b3c (patch) | |
tree | 9c4292da3c80b2894d5f2e055951e5df60871980 /doc/README.srio-pcie-boot-corenet | |
parent | 334b9b004c61f9a3f195968e6107f5362a29ce47 (diff) | |
download | u-boot-ba5da550ae1d955e53691e51cd74a27331ca3b3c.tar.xz |
i2c: designware_i2c: Add support for PCI(e) based I2C cores (x86)
This patch adds support for the PCI(e) based I2C cores. Which can be
found for example on the Intel Bay Trail SoC. It has 7 I2C controllers
implemented as PCI devices.
This patch also adds the fixed values for the timing registers for
BayTrail which are taken from the Linux designware I2C driver.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'doc/README.srio-pcie-boot-corenet')
0 files changed, 0 insertions, 0 deletions