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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2015-06-04 04:38:50 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-06-15 14:57:27 (GMT) |
| commit | c997da5c53586e0cb220d94179f922e865cffb62 (patch) | |
| tree | fa43c37a6848a8b6067694d3d62f246ee15a72e1 /doc/README.switch_config | |
| parent | 2ce6ecaccaa0b1bea31cdbe05f5f5c54d2468db0 (diff) | |
| download | u-boot-c997da5c53586e0cb220d94179f922e865cffb62.tar.xz | |
ARM: DRA7: emif: Fix DDR init sequence during warm reset
Unlike OMAP5, EMIF PHY used in DRA7 will be left in unknown state after
warm reset, emif needs to be configured to bring it back to a known
state. So configure EMIF during warm reset.
Reported-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'doc/README.switch_config')
0 files changed, 0 insertions, 0 deletions