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authorMarek Vasut <marex@denx.de>2014-10-22 19:56:03 (GMT)
committerJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>2014-10-27 17:07:03 (GMT)
commitdf155672ff262dd779ef12c04d9fc1911b778990 (patch)
treea4504d4a720f93744d28aefc170e99138e8b11db /doc
parentbc76b821f05fa4cdfca406cba975657de7a8e9f8 (diff)
downloadu-boot-df155672ff262dd779ef12c04d9fc1911b778990.tar.xz
spi: altera: Add short note about EPCS/EPCQx1
Add short documentation-alike note on how to use the Altera SPI driver with the EPCS/EPCQx1 FPGA IP block on SoCFPGA Cyclone V into doc/SPI/README.altera_spi Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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+SoCFPGA EPCS/EPCQx1 mini howto:
+- Instantiate EPCS/EPCQx1 Serial flash controller in QSys and rebuild
+- The controller base address is the "Base" in QSys + 0x400
+- Set MSEL[4:0]=10010 (AS Standard)
+- Load the bitstream into FPGA, enable bridges
+- Only then will the driver work