diff options
| author | York Sun <yorksun@freescale.com> | 2015-01-06 21:18:50 (GMT) |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-02-24 21:09:18 (GMT) |
| commit | 03e664d8f4065010ccb6c75648192200a832fd8b (patch) | |
| tree | f0398fdcdc87e12da79a82cde310b1a11937641a /drivers/ddr/fsl/options.c | |
| parent | b87e6f88e9218da3de371bb6cc8a34924153178e (diff) | |
| download | u-boot-03e664d8f4065010ccb6c75648192200a832fd8b.tar.xz | |
driver/ddr/fsl: Add support for multiple DDR clocks
Controller number is passed for function calls to support individual
DDR clock, depending on SoC implementation. It is backward compatible
with exising platforms. Multiple clocks have been verifyed on LS2085A
emulator.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'drivers/ddr/fsl/options.c')
| -rw-r--r-- | drivers/ddr/fsl/options.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c index 6d098d1..5beb11b 100644 --- a/drivers/ddr/fsl/options.c +++ b/drivers/ddr/fsl/options.c @@ -732,7 +732,7 @@ unsigned int populate_memctl_options(int all_dimms_registered, #endif /* Global Timing Parameters. */ - debug("mclk_ps = %u ps\n", get_memory_clk_period_ps()); + debug("mclk_ps = %u ps\n", get_memory_clk_period_ps(ctrl_num)); /* Pick a caslat override. */ popts->cas_latency_override = 0; @@ -785,7 +785,7 @@ unsigned int populate_memctl_options(int all_dimms_registered, * FIXME: width, was considering looking at pdimm->primary_sdram_width */ #if defined(CONFIG_SYS_FSL_DDR1) - popts->tfaw_window_four_activates_ps = mclk_to_picos(1); + popts->tfaw_window_four_activates_ps = mclk_to_picos(ctrl_num, 1); #elif defined(CONFIG_SYS_FSL_DDR2) /* @@ -1036,7 +1036,7 @@ done: if (pdimm[0].n_ranks == 4) popts->quad_rank_present = 1; - ddr_freq = get_ddr_freq(0) / 1000000; + ddr_freq = get_ddr_freq(ctrl_num) / 1000000; if (popts->registered_dimm_en) { popts->rcw_override = 1; popts->rcw_1 = 0x000a5a00; |