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| author | York Sun <yorksun@freescale.com> | 2014-02-10 21:59:44 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-02-21 16:06:13 (GMT) |
| commit | 6b1e1254f326940e5b65c7029f71b964bdf28fd4 (patch) | |
| tree | a8e596b2d01fe4a952e253b9b42972b040a4a165 /drivers/ddr/fsl/util.c | |
| parent | 6b9e309a8a7f0f33252288f0ed8794a83a488301 (diff) | |
| download | u-boot-6b1e1254f326940e5b65c7029f71b964bdf28fd4.tar.xz | |
driver/ddr: Add 256 byte interleaving support
Freescale LayerScape SoCs support controller interleaving on 256 byte size.
This interleaving is mandoratory.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'drivers/ddr/fsl/util.c')
| -rw-r--r-- | drivers/ddr/fsl/util.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c index 450a488..ad53658 100644 --- a/drivers/ddr/fsl/util.c +++ b/drivers/ddr/fsl/util.c @@ -228,6 +228,9 @@ void board_add_ram_info(int use_default) puts(" DDR Controller Interleaving Mode: "); switch ((cs0_config >> 24) & 0xf) { + case FSL_DDR_256B_INTERLEAVING: + puts("256B"); + break; case FSL_DDR_CACHE_LINE_INTERLEAVING: puts("cache line"); break; |