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| author | York Sun <yorksun@freescale.com> | 2014-12-02 19:18:09 (GMT) |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-12-15 17:15:12 (GMT) |
| commit | 938bbb6013f051808c08204184e94d0cdcb6dbff (patch) | |
| tree | 8102d1ed2cb0ef18f642c606d4ade71219c62f64 /drivers/ddr/fsl/util.c | |
| parent | 84d13c58104ea121a8d38a1d9c71e404d8666875 (diff) | |
| download | u-boot-938bbb6013f051808c08204184e94d0cdcb6dbff.tar.xz | |
driver/ddr/fsl: Fix MRC_CYC calculation for DDR3
For DDR controller version 4.7 or newer, MRC_CYC (mode register set
cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD
is max(12nCK, 15ns) according to JEDEC spec.
DDR4 is not affected by this change.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'drivers/ddr/fsl/util.c')
0 files changed, 0 insertions, 0 deletions