diff options
| author | Marek Vasut <marex@denx.de> | 2016-04-04 14:07:11 (GMT) |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2016-04-20 09:28:43 (GMT) |
| commit | abaf83619cb1bcb095400c4117bdd3ebbc764905 (patch) | |
| tree | 2c9e0d8bf57360b3a56d9dcd714b8ded1d8f8494 /drivers/ddr | |
| parent | 108f8418597350bd98357f25acaa8ab8a0435779 (diff) | |
| download | u-boot-abaf83619cb1bcb095400c4117bdd3ebbc764905.tar.xz | |
ddr: altera: Replace ad-hoc constant with macro
The bit 22 is in fact DQS tracking enable bit (dqstrken) and there
is a macro for this bit already, so use it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Diffstat (limited to 'drivers/ddr')
| -rw-r--r-- | drivers/ddr/altera/sequencer.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index 79c265f..34b1aa7 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -3486,7 +3486,7 @@ static int run_mem_calibrate(void) writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status); /* Stop tracking manager. */ - clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22); + clrbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK); phy_mgr_initialize(); rw_mgr_mem_initialize(); @@ -3507,7 +3507,7 @@ static int run_mem_calibrate(void) writel(0x2, &phy_mgr_cfg->mux_sel); /* Start tracking manager. */ - setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22); + setbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK); return pass; } |