diff options
| author | Simon Glass <sjg@chromium.org> | 2015-08-30 22:55:15 (GMT) |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-09-03 03:28:23 (GMT) |
| commit | e3563f2ec768fb989149362ca0c6ca4a27513924 (patch) | |
| tree | 0465a7e400294775fd034079802fccd82a1942ff /drivers/mmc/exynos_dw_mmc.c | |
| parent | 6a436c9182a90551739a5b7b3f44254234056915 (diff) | |
| download | u-boot-e3563f2ec768fb989149362ca0c6ca4a27513924.tar.xz | |
mmc: Support bypass mode with the get_mmc_clk() method
Some SoCs want to adjust the input clock to the DWMMC block as a way of
controlling the MMC bus clock. Update the get_mmc_clk() method to support
this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Diffstat (limited to 'drivers/mmc/exynos_dw_mmc.c')
| -rw-r--r-- | drivers/mmc/exynos_dw_mmc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index cde2ba7..863bbb3 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -39,7 +39,7 @@ static void exynos_dwmci_clksel(struct dwmci_host *host) dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing); } -unsigned int exynos_dwmci_get_clk(struct dwmci_host *host) +unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq) { unsigned long sclk; int8_t clk_div; |