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authorLiu Ying <Ying.Liu@freescale.com>2012-10-06 04:16:04 (GMT)
committerAnatolij Gustschin <agust@denx.de>2012-11-06 21:24:11 (GMT)
commit945d069fb5c8932e74aeba178c60a9dc6e9cba93 (patch)
tree6f8361c6771812663f2654467219bd7acd9dd513 /drivers/net/e1000.h
parent1cc619be8b73abbee2fd6faf2cd4ade27b516531 (diff)
downloadu-boot-945d069fb5c8932e74aeba178c60a9dc6e9cba93.tar.xz
ipu common: reset ipuv3 correctly
This patch checks self-clear sw_ipu_rst bit in SCR register of SRC controller to be cleared after setting it to high to reset IPUv3. This makes sure that IPUv3 finishes sofware reset. A timeout mechanism is added to stop polling on the bit status in case the bit could not be cleared by the hardware automatically within 10 millisecond. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Diffstat (limited to 'drivers/net/e1000.h')
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