diff options
| author | Simon Glass <sjg@chromium.org> | 2016-05-05 13:28:10 (GMT) |
|---|---|---|
| committer | Andreas Bießmann <andreas@biessmann.org> | 2016-06-12 21:49:38 (GMT) |
| commit | f589f8cca64bddb59fe2409c10ab14529ab47a40 (patch) | |
| tree | d04d7ee3227dda189c3e930e6c782d1fc9f091f7 /drivers/net | |
| parent | d5555b70e6cdbce4e1395f40c19a504015f93668 (diff) | |
| download | u-boot-f589f8cca64bddb59fe2409c10ab14529ab47a40.tar.xz | |
net: macb: Flush correct cache portion when sending
The end address of the cache flush must be cache-line-aligned since
otherwise (at least on ARM926-EJS) the request is ignored. When the cache
is enabled this means that packets are not sent.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/macb.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 8be62af..84bae37 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -280,7 +280,7 @@ static int _macb_send(struct macb_device *macb, const char *name, void *packet, barrier(); macb_flush_ring_desc(macb, TX); /* Do we need check paddr and length is dcache line aligned? */ - flush_dcache_range(paddr, paddr + length); + flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN)); macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART)); /* |