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| author | Tom Rini <trini@konsulko.com> | 2017-01-19 17:22:23 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-01-19 17:22:23 (GMT) |
| commit | 0675f992dbf4a785a05a1baf149c2bce6aa5fe90 (patch) | |
| tree | b8868ec70ff6b2b20f8f0fb87df9438906020a08 /drivers/pci/Kconfig | |
| parent | 755b06d1c0f3b16318c7580bec066efbb9ec6ccf (diff) | |
| parent | 5e4a6db8f428cb1f8ced74bc77241144ac0c5b1a (diff) | |
| download | u-boot-0675f992dbf4a785a05a1baf149c2bce6aa5fe90.tar.xz | |
Merge git://git.denx.de/u-boot-fsl-qoriq
Diffstat (limited to 'drivers/pci/Kconfig')
| -rw-r--r-- | drivers/pci/Kconfig | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 275b29b..692a398 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -71,4 +71,12 @@ config PCI_XILINX Enable support for the Xilinx AXI bridge for PCI express, an IP block which can be used on some generations of Xilinx FPGAs. +config PCIE_LAYERSCAPE + bool "Layerscape PCIe support" + depends on DM_PCI + help + Support Layerscape PCIe. The Layerscape SoC may have one or several + PCIe controllers. The PCIe may works in RC or EP mode according to + RCW[HOST_AGT_PEX] setting. + endif |