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| author | Simon Glass <sjg@chromium.org> | 2017-05-19 02:09:51 (GMT) |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2017-06-01 13:03:15 (GMT) |
| commit | bf501595cd5981b0196b51505ad50972b1c34cc4 (patch) | |
| tree | 03cac560f38955f8083db0e9c8f30d34e9f7d882 /drivers/pci | |
| parent | 40a475e8415a0fa3838e9d192507775d1d7fe754 (diff) | |
| download | u-boot-bf501595cd5981b0196b51505ad50972b1c34cc4.tar.xz | |
dm: pci: Update uclass to support livetree
Update the PCI uclass to support livetree. This mostly involves fixing
the address decoding from the device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/pci-uclass.c | 26 |
1 files changed, 12 insertions, 14 deletions
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 504d7e3..b36ef33 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -8,12 +8,11 @@ #include <common.h> #include <dm.h> #include <errno.h> -#include <fdtdec.h> #include <inttypes.h> #include <pci.h> #include <asm/io.h> -#include <dm/lists.h> #include <dm/device-internal.h> +#include <dm/lists.h> #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP) #include <asm/fsp/fsp_support.h> #endif @@ -754,8 +753,8 @@ error: return ret; } -static int decode_regions(struct pci_controller *hose, const void *blob, - int parent_node, int node) +static int decode_regions(struct pci_controller *hose, ofnode parent_node, + ofnode node) { int pci_addr_cells, addr_cells, size_cells; phys_addr_t base = 0, size; @@ -764,12 +763,12 @@ static int decode_regions(struct pci_controller *hose, const void *blob, int len; int i; - prop = fdt_getprop(blob, node, "ranges", &len); + prop = ofnode_read_prop(node, "ranges", &len); if (!prop) return -EINVAL; - pci_addr_cells = fdt_address_cells(blob, node); - addr_cells = fdt_address_cells(blob, parent_node); - size_cells = fdt_size_cells(blob, node); + pci_addr_cells = ofnode_read_addr_cells(node); + addr_cells = ofnode_read_addr_cells(parent_node); + size_cells = ofnode_read_size_cells(node); /* PCI addresses are always 3-cells */ len /= sizeof(u32); @@ -841,9 +840,8 @@ static int pci_uclass_pre_probe(struct udevice *bus) /* For bridges, use the top-level PCI controller */ if (!device_is_on_pci_bus(bus)) { hose->ctlr = bus; - ret = decode_regions(hose, gd->fdt_blob, - dev_of_offset(bus->parent), - dev_of_offset(bus)); + ret = decode_regions(hose, dev_ofnode(bus->parent), + dev_ofnode(bus)); if (ret) { debug("%s: Cannot decode regions\n", __func__); return ret; @@ -906,7 +904,7 @@ static int pci_uclass_child_post_bind(struct udevice *dev) struct fdt_pci_addr addr; int ret; - if (dev_of_offset(dev) == -1) + if (!dev_of_valid(dev)) return 0; /* @@ -914,8 +912,8 @@ static int pci_uclass_child_post_bind(struct udevice *dev) * just check the address. */ pplat = dev_get_parent_platdata(dev); - ret = fdtdec_get_pci_addr(gd->fdt_blob, dev_of_offset(dev), - FDT_PCI_SPACE_CONFIG, "reg", &addr); + ret = ofnode_read_pci_addr(dev_ofnode(dev), FDT_PCI_SPACE_CONFIG, "reg", + &addr); if (ret) { if (ret != -ENOENT) |