diff options
| author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2017-07-17 09:31:41 (GMT) |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2017-08-08 09:10:54 (GMT) |
| commit | f659554f2baf2a91708a228ba02c6a9045ae9641 (patch) | |
| tree | c044bd8febc3a0913f8ed595129e9f505e550426 /drivers/pci | |
| parent | e232b2d089c72ee4fc219b86d1ac5969d90d4a0c (diff) | |
| download | u-boot-f659554f2baf2a91708a228ba02c6a9045ae9641.tar.xz | |
PCI: layerscape: Fix the bug assigning wrong address to LS2088A pcie cfg1 space
This bug is brought by the commit 3d8553f0a3 (pci: layerscape: add
LS2088A series SoC pcie support), which only updated cfg_res.start
and did not update the .end field, this will make fdt_resource_size()
getting wrong value when calculate the cfg1 space address. This
patch is to fix the bug.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/pcie_layerscape.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 78cde21..610f85c 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -478,6 +478,7 @@ static int ls_pcie_probe(struct udevice *dev) bool ep_mode; uint svr; int ret; + fdt_size_t cfg_size; pcie->bus = dev; @@ -539,8 +540,10 @@ static int ls_pcie_probe(struct udevice *dev) if (svr == SVR_LS2088A || svr == SVR_LS2084A || svr == SVR_LS2048A || svr == SVR_LS2044A || svr == SVR_LS2081A || svr == SVR_LS2041A) { + cfg_size = fdt_resource_size(&pcie->cfg_res); pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR + LS2088A_PCIE_PHYS_SIZE * pcie->idx; + pcie->cfg_res.end = pcie->cfg_res.start + cfg_size; pcie->ctrl = pcie->lut + 0x40000; } |