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author | Peter Pearse <peter.pearse@arm.com> | 2007-05-18 13:33:23 (GMT) |
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committer | Peter Pearse <peter.pearse@arm.com> | 2007-05-18 13:33:23 (GMT) |
commit | fdda367561f0f6fb21d5b575402c0f9d2fd08e76 (patch) | |
tree | afb703e6e43ff91e6f456f12fbb43fb598373fd5 /drivers/systemace.c | |
parent | 1443a31457d68f7e8f0b9403e9832ec1e79dc59d (diff) | |
parent | 70124c2602ae2d4c5d3dba05b482d91548242de8 (diff) | |
download | u-boot-fdda367561f0f6fb21d5b575402c0f9d2fd08e76.tar.xz |
Merge with git://www.denx.de/git/u-boot.git
Diffstat (limited to 'drivers/systemace.c')
-rw-r--r-- | drivers/systemace.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/systemace.c b/drivers/systemace.c index 3848d9c..7d82c27 100644 --- a/drivers/systemace.c +++ b/drivers/systemace.c @@ -211,10 +211,16 @@ static unsigned long systemace_read(int dev, unsigned long start, /* Write sector count | ReadMemCardData. */ ace_writew((trans & 0xff) | 0x0300, 0x14); +/* + * For FPGA configuration via SystemACE is reset unacceptable + * CFGDONE bit in STATUSREG is not set to 1. + */ +#ifndef SYSTEMACE_CONFIG_FPGA /* Reset the configruation controller */ val = ace_readw(0x18); val |= 0x0080; ace_writew(val, 0x18); +#endif retry = trans * 16; while (retry > 0) { |