diff options
| author | Markus Klotzbuecher <mk@denx.de> | 2006-11-27 10:43:09 (GMT) |
|---|---|---|
| committer | Markus Klotzbuecher <mk@pollux.denx.de> | 2006-11-27 10:43:09 (GMT) |
| commit | 53e336e9ffc51035bdc4e5867631b3378761b4df (patch) | |
| tree | 77756a70bf7c5628bc5667da15abb97b396810a0 /drivers/usb_ohci.c | |
| parent | 98280e3d431db77d92219438b8840853bd7cb412 (diff) | |
| download | u-boot-53e336e9ffc51035bdc4e5867631b3378761b4df.tar.xz | |
Modified the mpc5xxx and the ppc4xx cpu to use the generic OHCI driver
and adapted board configs TQM5200 and yosemite accordingly. This commit
also makes the maximum number of root hub ports configurable
(CFG_USB_OHCI_MAX_ROOT_PORTS).
Diffstat (limited to 'drivers/usb_ohci.c')
| -rw-r--r-- | drivers/usb_ohci.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/drivers/usb_ohci.c b/drivers/usb_ohci.c index 9b3ca12..be1a615 100644 --- a/drivers/usb_ohci.c +++ b/drivers/usb_ohci.c @@ -45,6 +45,7 @@ #ifdef CONFIG_USB_OHCI +/* mk: are these really required? */ #if defined(CONFIG_S3C2400) # include <s3c2400.h> #elif defined(CONFIG_S3C2410) @@ -53,6 +54,8 @@ # include <asm/arch/hardware.h> #elif defined(CONFIG_CPU_MONAHANS) # include <asm/arch/pxa-regs.h> +#elif defined(CONFIG_MPC5200) +# include <mpc5xxx.h> #endif #include <malloc.h> @@ -557,8 +560,10 @@ static int ep_link (ohci_t *ohci, ed_t *edi) * the link from the ed still points to another operational ed or 0 * so the HC can eventually finish the processing of the unlinked ed */ -static int ep_unlink (ohci_t *ohci, ed_t *ed) +static int ep_unlink (ohci_t *ohci, ed_t *edi) { + volatile ed_t *ed = edi; + ed->hwINFO |= m32_swap (OHCI_ED_SKIP); switch (ed->type) { @@ -825,6 +830,9 @@ static td_t * dl_reverse_done_list (ohci_t *ohci) } else td_list->ed->hwHeadP &= m32_swap (0xfffffff2); } +#ifdef CONFIG_MPC5200 + td_list->hwNextTD = 0; +#endif } td_list->next_dl_td = td_rev; @@ -1448,7 +1456,8 @@ static int hc_reset (ohci_t *ohci) readl(&ohci->regs->control)); /* Reset USB (needed by some controllers) */ - writel (0, &ohci->regs->control); + ohci->hc_control = 0; + writel (ohci->hc_control, &ohci->regs->control); /* HC Reset requires max 10 us delay */ writel (OHCI_HCR, &ohci->regs->cmdstatus); |