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| author | Tom Rini <trini@konsulko.com> | 2015-03-02 02:06:33 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-03-02 02:06:33 (GMT) |
| commit | 00956eb5f313d0a62c39f4fa642ffbaa85cc955c (patch) | |
| tree | 3e30dd00af063f3f8bac6ad2c3f85d669b0d9506 /drivers | |
| parent | 55ca6138240b8c5b986e918aca4d96d402cc2f21 (diff) | |
| parent | c3dd82386493d67cc5b0de06876360a27224b620 (diff) | |
| download | u-boot-00956eb5f313d0a62c39f4fa642ffbaa85cc955c.tar.xz | |
Merge branch 'master' of git://git.denx.de/u-boot-sh
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/serial/serial_sh.c | 2 | ||||
| -rw-r--r-- | drivers/serial/serial_sh.h | 5 |
2 files changed, 4 insertions, 3 deletions
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index 3641c9f..8693c1e 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -69,7 +69,7 @@ sh_serial_setbrg_generic(struct uart_port *port, int clk, int baudrate) if (port->clk_mode == EXT_CLK) { unsigned short dl = DL_VALUE(baudrate, clk); sci_out(port, DL, dl); - /* Need wait: Clock * 1/dl × 1/16 */ + /* Need wait: Clock * 1/dl * 1/16 */ udelay((1000000 * dl * 16 / clk) * 1000 + 1); } else { sci_out(port, SCBRR, SCBRR_VALUE(baudrate, clk)); diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index 528aa73..941e6ed 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -227,7 +227,8 @@ struct uart_port { #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) # define SCIF_ORER 0x0001 -# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */ +# define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30) + /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */ #else # error CPU subtype not defined #endif @@ -742,7 +743,7 @@ static inline int scbrr_calc(struct uart_port *port, int bps, int clk) #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */ -#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) /* Internal Clock */ +#define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */ #else /* Generic SH */ #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) #endif |