Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

23 files changed, 1219 insertions, 210 deletions

diff --git a/drivers/crypto/fsl/fsl_blob.c b/drivers/crypto/fsl/fsl_blob.c
index bc01075..9923bcb 100644
--- a/drivers/crypto/fsl/fsl_blob.c
+++ b/drivers/crypto/fsl/fsl_blob.c
@@ -11,7 +11,7 @@
 #include "desc.h"
 #include "jr.h"
 
-int blob_decrypt(u8 *key_mod, u8 *src, u8 *dst, u8 len)
+int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
 {
 	int ret, i = 0;
 	u32 *desc;
@@ -36,7 +36,7 @@ int blob_decrypt(u8 *key_mod, u8 *src, u8 *dst, u8 len)
 	return ret;
 }
 
-int blob_encrypt(u8 *key_mod, u8 *src, u8 *dst, u8 len)
+int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
 {
 	int ret, i = 0;
 	u32 *desc;
diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c
index d77f257..c298404 100644
--- a/drivers/crypto/fsl/fsl_hash.c
+++ b/drivers/crypto/fsl/fsl_hash.c
@@ -10,6 +10,9 @@
 #include "jobdesc.h"
 #include "desc.h"
 #include "jr.h"
+#include "fsl_hash.h"
+#include <hw_sha.h>
+#include <asm-generic/errno.h>
 
 #define CRYPTO_MAX_ALG_NAME	80
 #define SHA1_DIGEST_SIZE        20
@@ -39,6 +42,122 @@ static struct caam_hash_template driver_hash[] = {
 	},
 };
 
+static enum caam_hash_algos get_hash_type(struct hash_algo *algo)
+{
+	if (!strcmp(algo->name, driver_hash[SHA1].name))
+		return SHA1;
+	else
+		return SHA256;
+}
+
+/* Create the context for progressive hashing using h/w acceleration.
+ *
+ * @ctxp: Pointer to the pointer of the context for hashing
+ * @caam_algo: Enum for SHA1 or SHA256
+ * @return 0 if ok, -ENOMEM on error
+ */
+static int caam_hash_init(void **ctxp, enum caam_hash_algos caam_algo)
+{
+	*ctxp = calloc(1, sizeof(struct sha_ctx));
+	if (*ctxp == NULL) {
+		debug("Cannot allocate memory for context\n");
+		return -ENOMEM;
+	}
+	return 0;
+}
+
+/*
+ * Update sg table for progressive hashing using h/w acceleration
+ *
+ * The context is freed by this function if an error occurs.
+ * We support at most 32 Scatter/Gather Entries.
+ *
+ * @hash_ctx: Pointer to the context for hashing
+ * @buf: Pointer to the buffer being hashed
+ * @size: Size of the buffer being hashed
+ * @is_last: 1 if this is the last update; 0 otherwise
+ * @caam_algo: Enum for SHA1 or SHA256
+ * @return 0 if ok, -EINVAL on error
+ */
+static int caam_hash_update(void *hash_ctx, const void *buf,
+			    unsigned int size, int is_last,
+			    enum caam_hash_algos caam_algo)
+{
+	uint32_t final = 0;
+	dma_addr_t addr = virt_to_phys((void *)buf);
+	struct sha_ctx *ctx = hash_ctx;
+
+	if (ctx->sg_num >= MAX_SG_32) {
+		free(ctx);
+		return -EINVAL;
+	}
+
+#ifdef CONFIG_PHYS_64BIT
+	ctx->sg_tbl[ctx->sg_num].addr_hi = addr >> 32;
+#else
+	ctx->sg_tbl[ctx->sg_num].addr_hi = 0x0;
+#endif
+	ctx->sg_tbl[ctx->sg_num].addr_lo = addr;
+
+	sec_out32(&ctx->sg_tbl[ctx->sg_num].len_flag,
+		  (size & SG_ENTRY_LENGTH_MASK));
+
+	ctx->sg_num++;
+
+	if (is_last) {
+		final = sec_in32(&ctx->sg_tbl[ctx->sg_num - 1].len_flag) |
+			SG_ENTRY_FINAL_BIT;
+		sec_out32(&ctx->sg_tbl[ctx->sg_num - 1].len_flag, final);
+	}
+
+	return 0;
+}
+
+/*
+ * Perform progressive hashing on the given buffer and copy hash at
+ * destination buffer
+ *
+ * The context is freed after completion of hash operation.
+ *
+ * @hash_ctx: Pointer to the context for hashing
+ * @dest_buf: Pointer to the destination buffer where hash is to be copied
+ * @size: Size of the buffer being hashed
+ * @caam_algo: Enum for SHA1 or SHA256
+ * @return 0 if ok, -EINVAL on error
+ */
+static int caam_hash_finish(void *hash_ctx, void *dest_buf,
+			    int size, enum caam_hash_algos caam_algo)
+{
+	uint32_t len = 0;
+	struct sha_ctx *ctx = hash_ctx;
+	int i = 0, ret = 0;
+
+	if (size < driver_hash[caam_algo].digestsize) {
+		free(ctx);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < ctx->sg_num; i++)
+		len += (sec_in32(&ctx->sg_tbl[i].len_flag) &
+			SG_ENTRY_LENGTH_MASK);
+
+	inline_cnstr_jobdesc_hash(ctx->sha_desc, (uint8_t *)ctx->sg_tbl, len,
+				  ctx->hash,
+				  driver_hash[caam_algo].alg_type,
+				  driver_hash[caam_algo].digestsize,
+				  1);
+
+	ret = run_descriptor_jr(ctx->sha_desc);
+
+	if (ret)
+		debug("Error %x\n", ret);
+	else
+		memcpy(dest_buf, ctx->hash, sizeof(ctx->hash));
+
+	free(ctx);
+	return ret;
+}
+
 int caam_hash(const unsigned char *pbuf, unsigned int buf_len,
 	      unsigned char *pout, enum caam_hash_algos algo)
 {
@@ -48,7 +167,7 @@ int caam_hash(const unsigned char *pbuf, unsigned int buf_len,
 	desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE);
 	if (!desc) {
 		debug("Not enough memory for descriptor allocation\n");
-		return -1;
+		return -ENOMEM;
 	}
 
 	inline_cnstr_jobdesc_hash(desc, pbuf, buf_len, pout,
@@ -75,3 +194,20 @@ void hw_sha1(const unsigned char *pbuf, unsigned int buf_len,
 	if (caam_hash(pbuf, buf_len, pout, SHA1))
 		printf("CAAM was not setup properly or it is faulty\n");
 }
+
+int hw_sha_init(struct hash_algo *algo, void **ctxp)
+{
+	return caam_hash_init(ctxp, get_hash_type(algo));
+}
+
+int hw_sha_update(struct hash_algo *algo, void *ctx, const void *buf,
+			    unsigned int size, int is_last)
+{
+	return caam_hash_update(ctx, buf, size, is_last, get_hash_type(algo));
+}
+
+int hw_sha_finish(struct hash_algo *algo, void *ctx, void *dest_buf,
+		     int size)
+{
+	return caam_hash_finish(ctx, dest_buf, size, get_hash_type(algo));
+}
diff --git a/drivers/crypto/fsl/fsl_hash.h b/drivers/crypto/fsl/fsl_hash.h
new file mode 100644
index 0000000..f5be651
--- /dev/null
+++ b/drivers/crypto/fsl/fsl_hash.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#ifndef _SHA_H
+#define _SHA_H
+
+#include <fsl_sec.h>
+#include <hash.h>
+#include "jr.h"
+
+/* We support at most 32 Scatter/Gather Entries.*/
+#define MAX_SG_32	32
+
+/*
+ * Hash context contains the following fields
+ * @sha_desc: Sha Descriptor
+ * @sg_num: number of entries in sg table
+ * @len: total length of buffer
+ * @sg_tbl: sg entry table
+ * @hash: index to the hash calculated
+ */
+struct sha_ctx {
+	uint32_t sha_desc[64];
+	uint32_t sg_num;
+	uint32_t len;
+	struct sg_entry sg_tbl[MAX_SG_32];
+	u8 hash[HASH_MAX_DIGEST_SIZE];
+};
+
+#endif
diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c
index c139da6..7160da4 100644
--- a/drivers/ddr/fsl/arm_ddr_gen3.c
+++ b/drivers/ddr/fsl/arm_ddr_gen3.c
@@ -222,7 +222,7 @@ step2:
 	bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
 			>> SDRAM_CFG_DBW_SHIFT);
 	timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
-		(get_ddr_freq(0) >> 20)) << 1;
+		(get_ddr_freq(ctrl_num) >> 20)) << 1;
 	total_gb_size_per_controller >>= 4;	/* shift down to gb size */
 	debug("total %d GB\n", total_gb_size_per_controller);
 	debug("Need to wait up to %d * 10ms\n", timeout);
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 03d7ff1..690e73d 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -17,8 +17,6 @@
 #include <fsl_immap.h>
 #include <asm/io.h>
 
-unsigned int picos_to_mclk(unsigned int picos);
-
 /*
  * Determine Rtt value.
  *
@@ -78,10 +76,11 @@ static inline int fsl_ddr_get_rtt(void)
  *       16 for <= 2933MT/s
  *       18 for higher
  */
-static inline unsigned int compute_cas_write_latency(void)
+static inline unsigned int compute_cas_write_latency(
+				const unsigned int ctrl_num)
 {
 	unsigned int cwl;
-	const unsigned int mclk_ps = get_memory_clk_period_ps();
+	const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 	if (mclk_ps >= 1250)
 		cwl = 9;
 	else if (mclk_ps >= 1070)
@@ -111,10 +110,11 @@ static inline unsigned int compute_cas_write_latency(void)
  *       11 if 0.935ns > tCK >= 0.833ns
  *       12 if 0.833ns > tCK >= 0.75ns
  */
-static inline unsigned int compute_cas_write_latency(void)
+static inline unsigned int compute_cas_write_latency(
+				const unsigned int ctrl_num)
 {
 	unsigned int cwl;
-	const unsigned int mclk_ps = get_memory_clk_period_ps();
+	const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 
 	if (mclk_ps >= 2500)
 		cwl = 5;
@@ -287,7 +287,8 @@ static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
  * Avoid writing for DDR I.  The new PQ38 DDR controller
  * dreams up non-zero default values to be backwards compatible.
  */
-static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
+static void set_timing_cfg_0(const unsigned int ctrl_num,
+				fsl_ddr_cfg_regs_t *ddr,
 				const memctl_options_t *popts,
 				const dimm_params_t *dimm_params)
 {
@@ -306,7 +307,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 	/* Mode register set cycle time (tMRD). */
 	unsigned char tmrd_mclk;
 #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
-	const unsigned int mclk_ps = get_memory_clk_period_ps();
+	const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 #endif
 
 #ifdef CONFIG_SYS_FSL_DDR4
@@ -314,15 +315,15 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 	int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
 	trwt_mclk = 2;
 	twrt_mclk = 1;
-	act_pd_exit_mclk = picos_to_mclk(txp);
+	act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
 	pre_pd_exit_mclk = act_pd_exit_mclk;
 	/*
 	 * MRS_CYC = max(tMRD, tMOD)
 	 * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
 	 */
-	tmrd_mclk = max(24U, picos_to_mclk(15000));
+	tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000));
 #elif defined(CONFIG_SYS_FSL_DDR3)
-	unsigned int data_rate = get_ddr_freq(0);
+	unsigned int data_rate = get_ddr_freq(ctrl_num);
 	int txp;
 	unsigned int ip_rev;
 	int odt_overlap;
@@ -344,7 +345,8 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 		 * tMRD = 4nCK (8nCK for RDIMM)
 		 * tMOD = max(12nCK, 15ns)
 		 */
-		tmrd_mclk = max((unsigned int)12, picos_to_mclk(15000));
+		tmrd_mclk = max((unsigned int)12,
+				picos_to_mclk(ctrl_num, 15000));
 	} else {
 		/*
 		 * MRS_CYC = tMRD
@@ -388,7 +390,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 		taxpd_mclk = 1;
 	} else {
 		/* act_pd_exit_mclk = tXARD, see above */
-		act_pd_exit_mclk = picos_to_mclk(txp);
+		act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
 		/* Mode register MR0[A12] is '1' - fast exit */
 		pre_pd_exit_mclk = act_pd_exit_mclk;
 		taxpd_mclk = 1;
@@ -424,11 +426,12 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 #endif	/* !defined(CONFIG_SYS_FSL_DDR1) */
 
 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
-static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
-			       const memctl_options_t *popts,
-			       const common_timing_params_t *common_dimm,
-			       unsigned int cas_latency,
-			       unsigned int additive_latency)
+static void set_timing_cfg_3(const unsigned int ctrl_num,
+			     fsl_ddr_cfg_regs_t *ddr,
+			     const memctl_options_t *popts,
+			     const common_timing_params_t *common_dimm,
+			     unsigned int cas_latency,
+			     unsigned int additive_latency)
 {
 	/* Extended precharge to activate interval (tRP) */
 	unsigned int ext_pretoact = 0;
@@ -447,18 +450,18 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
 	/* Control Adjust */
 	unsigned int cntl_adj = 0;
 
-	ext_pretoact = picos_to_mclk(common_dimm->trp_ps) >> 4;
-	ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4;
-	ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4;
+	ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4;
+	ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4;
+	ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4;
 	ext_caslat = (2 * cas_latency - 1) >> 4;
 	ext_add_lat = additive_latency >> 4;
 #ifdef CONFIG_SYS_FSL_DDR4
-	ext_refrec = (picos_to_mclk(common_dimm->trfc1_ps) - 8) >> 4;
+	ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4;
 #else
-	ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4;
+	ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4;
 	/* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
 #endif
-	ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) +
+	ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) +
 		(popts->otf_burst_chop_en ? 2 : 0)) >> 4;
 
 	ddr->timing_cfg_3 = (0
@@ -475,10 +478,11 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
 }
 
 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
-static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
-			       const memctl_options_t *popts,
-			       const common_timing_params_t *common_dimm,
-			       unsigned int cas_latency)
+static void set_timing_cfg_1(const unsigned int ctrl_num,
+			     fsl_ddr_cfg_regs_t *ddr,
+			     const memctl_options_t *popts,
+			     const common_timing_params_t *common_dimm,
+			     unsigned int cas_latency)
 {
 	/* Precharge-to-activate interval (tRP) */
 	unsigned char pretoact_mclk;
@@ -510,9 +514,9 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 		1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
 #endif
 
-	pretoact_mclk = picos_to_mclk(common_dimm->trp_ps);
-	acttopre_mclk = picos_to_mclk(common_dimm->tras_ps);
-	acttorw_mclk = picos_to_mclk(common_dimm->trcd_ps);
+	pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps);
+	acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps);
+	acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps);
 
 	/*
 	 * Translate CAS Latency to a DDR controller field value:
@@ -547,19 +551,19 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 #endif
 
 #ifdef CONFIG_SYS_FSL_DDR4
-	refrec_ctrl = picos_to_mclk(common_dimm->trfc1_ps) - 8;
-	wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
-	acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4U);
-	wrtord_mclk = max(2U, picos_to_mclk(2500));
+	refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8;
+	wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
+	acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U);
+	wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500));
 	if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
 		printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
 	else
 		wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 #else
-	refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8;
-	wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
-	acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps);
-	wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps);
+	refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8;
+	wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
+	acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps);
+	wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps);
 	if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
 		printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
 	else
@@ -602,11 +606,12 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 }
 
 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
-static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
-			       const memctl_options_t *popts,
-			       const common_timing_params_t *common_dimm,
-			       unsigned int cas_latency,
-			       unsigned int additive_latency)
+static void set_timing_cfg_2(const unsigned int ctrl_num,
+			     fsl_ddr_cfg_regs_t *ddr,
+			     const memctl_options_t *popts,
+			     const common_timing_params_t *common_dimm,
+			     unsigned int cas_latency,
+			     unsigned int additive_latency)
 {
 	/* Additive latency */
 	unsigned char add_lat_mclk;
@@ -623,7 +628,7 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 	/* Window for four activates (tFAW) */
 	unsigned short four_act;
 #ifdef CONFIG_SYS_FSL_DDR3
-	const unsigned int mclk_ps = get_memory_clk_period_ps();
+	const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 #endif
 
 	/* FIXME add check that this must be less than acttorw_mclk */
@@ -641,13 +646,13 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 #elif defined(CONFIG_SYS_FSL_DDR2)
 	wr_lat = cas_latency - 1;
 #else
-	wr_lat = compute_cas_write_latency();
+	wr_lat = compute_cas_write_latency(ctrl_num);
 #endif
 
 #ifdef CONFIG_SYS_FSL_DDR4
-	rd_to_pre = picos_to_mclk(7500);
+	rd_to_pre = picos_to_mclk(ctrl_num, 7500);
 #else
-	rd_to_pre = picos_to_mclk(common_dimm->trtp_ps);
+	rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps);
 #endif
 	/*
 	 * JEDEC has some min requirements for tRTP
@@ -665,19 +670,20 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 	wr_data_delay = popts->write_data_delay;
 #ifdef CONFIG_SYS_FSL_DDR4
 	cpo = 0;
-	cke_pls = max(3U, picos_to_mclk(5000));
+	cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000));
 #elif defined(CONFIG_SYS_FSL_DDR3)
 	/*
 	 * cke pulse = max(3nCK, 7.5ns) for DDR3-800
 	 *             max(3nCK, 5.625ns) for DDR3-1066, 1333
 	 *             max(3nCK, 5ns) for DDR3-1600, 1866, 2133
 	 */
-	cke_pls = max(3U, picos_to_mclk(mclk_ps > 1870 ? 7500 :
-				       (mclk_ps > 1245 ? 5625 : 5000)));
+	cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 :
+					(mclk_ps > 1245 ? 5625 : 5000)));
 #else
 	cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
 #endif
-	four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps);
+	four_act = picos_to_mclk(ctrl_num,
+				 popts->tfaw_window_four_activates_ps);
 
 	ddr->timing_cfg_2 = (0
 		| ((add_lat_mclk & 0xf) << 28)
@@ -818,7 +824,8 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 }
 
 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
-static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
+			       fsl_ddr_cfg_regs_t *ddr,
 			       const memctl_options_t *popts,
 			       const unsigned int unq_mrs_en)
 {
@@ -865,7 +872,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 #endif
 
 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
-	slow = get_ddr_freq(0) < 1249000000;
+	slow = get_ddr_freq(ctrl_num) < 1249000000;
 #endif
 
 	if (popts->registered_dimm_en) {
@@ -915,7 +922,8 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 
 #ifdef CONFIG_SYS_FSL_DDR4
 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
-static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
+				fsl_ddr_cfg_regs_t *ddr,
 				const memctl_options_t *popts,
 				const common_timing_params_t *common_dimm,
 				const unsigned int unq_mrs_en)
@@ -926,10 +934,10 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 	unsigned int wr_crc = 0;	/* Disable */
 	unsigned int rtt_wr = 0;	/* Rtt_WR - dynamic ODT off */
 	unsigned int srt = 0;	/* self-refresh temerature, normal range */
-	unsigned int cwl = compute_cas_write_latency() - 9;
+	unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9;
 	unsigned int mpr = 0;	/* serial */
 	unsigned int wc_lat;
-	const unsigned int mclk_ps = get_memory_clk_period_ps();
+	const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 
 	if (popts->rtt_override)
 		rtt_wr = popts->rtt_wr_override_value;
@@ -1002,7 +1010,8 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 }
 #elif defined(CONFIG_SYS_FSL_DDR3)
 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
-static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
+				fsl_ddr_cfg_regs_t *ddr,
 				const memctl_options_t *popts,
 				const common_timing_params_t *common_dimm,
 				const unsigned int unq_mrs_en)
@@ -1013,7 +1022,7 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 	unsigned int rtt_wr = 0;	/* Rtt_WR - dynamic ODT off */
 	unsigned int srt = 0;	/* self-refresh temerature, normal range */
 	unsigned int asr = 0;	/* auto self-refresh disable */
-	unsigned int cwl = compute_cas_write_latency() - 5;
+	unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5;
 	unsigned int pasr = 0;	/* partial array self refresh disable */
 
 	if (popts->rtt_override)
@@ -1077,7 +1086,8 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 
 #else /* for DDR2 and DDR1 */
 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
-static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
+				fsl_ddr_cfg_regs_t *ddr,
 				const memctl_options_t *popts,
 				const common_timing_params_t *common_dimm,
 				const unsigned int unq_mrs_en)
@@ -1144,7 +1154,8 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
 }
 
 /* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
-static void set_ddr_sdram_mode_10(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
+				fsl_ddr_cfg_regs_t *ddr,
 				const memctl_options_t *popts,
 				const common_timing_params_t *common_dimm,
 				const unsigned int unq_mrs_en)
@@ -1152,7 +1163,7 @@ static void set_ddr_sdram_mode_10(fsl_ddr_cfg_regs_t *ddr,
 	int i;
 	unsigned short esdmode6 = 0;	/* Extended SDRAM mode 6 */
 	unsigned short esdmode7 = 0;	/* Extended SDRAM mode 7 */
-	unsigned int tccdl_min = picos_to_mclk(common_dimm->tccdl_ps);
+	unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
 
 	esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
 
@@ -1196,14 +1207,15 @@ static void set_ddr_sdram_mode_10(fsl_ddr_cfg_regs_t *ddr,
 #endif
 
 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
-static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
-			       const memctl_options_t *popts,
-			       const common_timing_params_t *common_dimm)
+static void set_ddr_sdram_interval(const unsigned int ctrl_num,
+				fsl_ddr_cfg_regs_t *ddr,
+				const memctl_options_t *popts,
+				const common_timing_params_t *common_dimm)
 {
 	unsigned int refint;	/* Refresh interval */
 	unsigned int bstopre;	/* Precharge interval */
 
-	refint = picos_to_mclk(common_dimm->refresh_rate_ps);
+	refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps);
 
 	bstopre = popts->bstopre;
 
@@ -1217,7 +1229,8 @@ static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
 
 #ifdef CONFIG_SYS_FSL_DDR4
 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
-static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode(const unsigned int ctrl_num,
+			       fsl_ddr_cfg_regs_t *ddr,
 			       const memctl_options_t *popts,
 			       const common_timing_params_t *common_dimm,
 			       unsigned int cas_latency,
@@ -1292,7 +1305,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 	 * 1=fast exit DLL on (tXP)
 	 */
 
-	wr_mclk = picos_to_mclk(common_dimm->twr_ps);
+	wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
 	if (wr_mclk <= 24) {
 		wr = wr_table[wr_mclk - 10];
 	} else {
@@ -1387,7 +1400,8 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 
 #elif defined(CONFIG_SYS_FSL_DDR3)
 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
-static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode(const unsigned int ctrl_num,
+			       fsl_ddr_cfg_regs_t *ddr,
 			       const memctl_options_t *popts,
 			       const common_timing_params_t *common_dimm,
 			       unsigned int cas_latency,
@@ -1466,7 +1480,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 	 */
 	dll_on = 1;
 
-	wr_mclk = picos_to_mclk(common_dimm->twr_ps);
+	wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
 	if (wr_mclk <= 16) {
 		wr = wr_table[wr_mclk - 5];
 	} else {
@@ -1582,7 +1596,8 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 #else /* !CONFIG_SYS_FSL_DDR3 */
 
 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
-static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode(const unsigned int ctrl_num,
+			       fsl_ddr_cfg_regs_t *ddr,
 			       const memctl_options_t *popts,
 			       const common_timing_params_t *common_dimm,
 			       unsigned int cas_latency,
@@ -1654,7 +1669,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 #if defined(CONFIG_SYS_FSL_DDR1)
 	wr = 0;       /* Historical */
 #elif defined(CONFIG_SYS_FSL_DDR2)
-	wr = picos_to_mclk(common_dimm->twr_ps);
+	wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
 #endif
 	dll_res = 0;
 	mode = 0;
@@ -1842,15 +1857,16 @@ static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr)
 	debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
 }
 
-static void set_timing_cfg_7(fsl_ddr_cfg_regs_t *ddr,
-			const common_timing_params_t *common_dimm)
+static void set_timing_cfg_7(const unsigned int ctrl_num,
+			     fsl_ddr_cfg_regs_t *ddr,
+			     const common_timing_params_t *common_dimm)
 {
 	unsigned int txpr, tcksre, tcksrx;
 	unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd;
 
-	txpr = max(5U, picos_to_mclk(common_dimm->trfc1_ps + 10000));
-	tcksre = max(5U, picos_to_mclk(10000));
-	tcksrx = max(5U, picos_to_mclk(10000));
+	txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000));
+	tcksre = max(5U, picos_to_mclk(ctrl_num, 10000));
+	tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000));
 	par_lat = 0;
 	cs_to_cmd = 0;
 
@@ -1883,14 +1899,15 @@ static void set_timing_cfg_7(fsl_ddr_cfg_regs_t *ddr,
 	debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
 }
 
-static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr,
+static void set_timing_cfg_8(const unsigned int ctrl_num,
+			     fsl_ddr_cfg_regs_t *ddr,
 			     const memctl_options_t *popts,
 			     const common_timing_params_t *common_dimm,
 			     unsigned int cas_latency)
 {
 	unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
 	unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
-	unsigned int tccdl = picos_to_mclk(common_dimm->tccdl_ps);
+	unsigned int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
 	unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
 			      ((ddr->timing_cfg_2 & 0x00040000) >> 14);
 
@@ -1911,11 +1928,11 @@ static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr,
 		wwt_bg = tccdl - 4;
 	} else {
 		rrt_bg = tccdl - 2;
-		wwt_bg = tccdl - 4;
+		wwt_bg = tccdl - 2;
 	}
 
-	acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps);
-	wrtord_bg = max(4U, picos_to_mclk(7500));
+	acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps);
+	wrtord_bg = max(4U, picos_to_mclk(ctrl_num, 7500));
 	if (popts->otf_burst_chop_en)
 		wrtord_bg += 2;
 
@@ -2147,7 +2164,8 @@ check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
 }
 
 unsigned int
-compute_fsl_memctl_config_regs(const memctl_options_t *popts,
+compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
+			       const memctl_options_t *popts,
 			       fsl_ddr_cfg_regs_t *ddr,
 			       const common_timing_params_t *common_dimm,
 			       const dimm_params_t *dimm_params,
@@ -2319,14 +2337,14 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 	set_ddr_eor(ddr, popts);
 
 #if !defined(CONFIG_SYS_FSL_DDR1)
-	set_timing_cfg_0(ddr, popts, dimm_params);
+	set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params);
 #endif
 
-	set_timing_cfg_3(ddr, popts, common_dimm, cas_latency,
+	set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency,
 			 additive_latency);
-	set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
-	set_timing_cfg_2(ddr, popts, common_dimm,
-				cas_latency, additive_latency);
+	set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency);
+	set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm,
+			 cas_latency, additive_latency);
 
 	set_ddr_cdr1(ddr, popts);
 	set_ddr_cdr2(ddr, popts);
@@ -2338,15 +2356,15 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 	if ((ip_rev > 0x40700) && (popts->cswl_override != 0))
 		ddr->debug[18] = popts->cswl_override;
 
-	set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
-	set_ddr_sdram_mode(ddr, popts, common_dimm,
-				cas_latency, additive_latency, unq_mrs_en);
-	set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en);
+	set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en);
+	set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm,
+			   cas_latency, additive_latency, unq_mrs_en);
+	set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
 #ifdef CONFIG_SYS_FSL_DDR4
 	set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
-	set_ddr_sdram_mode_10(ddr, popts, common_dimm, unq_mrs_en);
+	set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
 #endif
-	set_ddr_sdram_interval(ddr, popts, common_dimm);
+	set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm);
 	set_ddr_data_init(ddr);
 	set_ddr_sdram_clk_cntl(ddr, popts);
 	set_ddr_init_addr(ddr);
@@ -2356,8 +2374,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 #ifdef CONFIG_SYS_FSL_DDR4
 	set_ddr_sdram_cfg_3(ddr, popts);
 	set_timing_cfg_6(ddr);
-	set_timing_cfg_7(ddr, common_dimm);
-	set_timing_cfg_8(ddr, popts, common_dimm, cas_latency);
+	set_timing_cfg_7(ctrl_num, ddr, common_dimm);
+	set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency);
 	set_timing_cfg_9(ddr);
 	set_ddr_dq_mapping(ddr, dimm_params);
 #endif
@@ -2372,7 +2390,11 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 #ifdef CONFIG_SYS_FSL_DDR_EMU
 	/* disble DDR training for emulator */
 	ddr->debug[2] = 0x00000400;
-	ddr->debug[4] = 0xff800000;
+	ddr->debug[4] = 0xff800800;
+	ddr->debug[5] = 0x08000800;
+	ddr->debug[6] = 0x08000800;
+	ddr->debug[7] = 0x08000800;
+	ddr->debug[8] = 0x08000800;
 #endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A004508
 	if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))
diff --git a/drivers/ddr/fsl/ddr1_dimm_params.c b/drivers/ddr/fsl/ddr1_dimm_params.c
index 7df27b9..7f1c3af 100644
--- a/drivers/ddr/fsl/ddr1_dimm_params.c
+++ b/drivers/ddr/fsl/ddr1_dimm_params.c
@@ -228,10 +228,10 @@ compute_derated_DDR1_CAS_latency(unsigned int mclk_ps)
  *
  * FIXME: use #define for the retvals
  */
-unsigned int
-ddr_compute_dimm_parameters(const ddr1_spd_eeprom_t *spd,
-			     dimm_params_t *pdimm,
-			     unsigned int dimm_number)
+unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
+					 const ddr1_spd_eeprom_t *spd,
+					 dimm_params_t *pdimm,
+					 unsigned int dimm_number)
 {
 	unsigned int retval;
 
@@ -311,16 +311,16 @@ ddr_compute_dimm_parameters(const ddr1_spd_eeprom_t *spd,
 					  & ~(1 << pdimm->caslat_x_minus_1));
 
 	/* Compute CAS latencies below that defined by SPD */
-	pdimm->caslat_lowest_derated
-		= compute_derated_DDR1_CAS_latency(get_memory_clk_period_ps());
+	pdimm->caslat_lowest_derated = compute_derated_DDR1_CAS_latency(
+					get_memory_clk_period_ps(ctrl_num));
 
 	/* Compute timing parameters */
 	pdimm->trcd_ps = spd->trcd * 250;
 	pdimm->trp_ps = spd->trp * 250;
 	pdimm->tras_ps = spd->tras * 1000;
 
-	pdimm->twr_ps = mclk_to_picos(3);
-	pdimm->twtr_ps = mclk_to_picos(1);
+	pdimm->twr_ps = mclk_to_picos(ctrl_num, 3);
+	pdimm->twtr_ps = mclk_to_picos(ctrl_num, 1);
 	pdimm->trfc_ps = compute_trfc_ps_from_spd(0, spd->trfc);
 
 	pdimm->trrd_ps = spd->trrd * 250;
@@ -335,7 +335,7 @@ ddr_compute_dimm_parameters(const ddr1_spd_eeprom_t *spd,
 	pdimm->tdh_ps
 		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
 
-	pdimm->trtp_ps = mclk_to_picos(2);	/* By the book. */
+	pdimm->trtp_ps = mclk_to_picos(ctrl_num, 2);	/* By the book. */
 	pdimm->tdqsq_max_ps = spd->tdqsq * 10;
 	pdimm->tqhs_ps = spd->tqhs * 10;
 
diff --git a/drivers/ddr/fsl/ddr2_dimm_params.c b/drivers/ddr/fsl/ddr2_dimm_params.c
index d865df7..49cc1a0 100644
--- a/drivers/ddr/fsl/ddr2_dimm_params.c
+++ b/drivers/ddr/fsl/ddr2_dimm_params.c
@@ -211,10 +211,10 @@ compute_derated_DDR2_CAS_latency(unsigned int mclk_ps)
  *
  * FIXME: use #define for the retvals
  */
-unsigned int
-ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd,
-			     dimm_params_t *pdimm,
-			     unsigned int dimm_number)
+unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
+					 const ddr2_spd_eeprom_t *spd,
+					 dimm_params_t *pdimm,
+					 unsigned int dimm_number)
 {
 	unsigned int retval;
 
@@ -310,8 +310,8 @@ ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd,
 					  & ~(1 << pdimm->caslat_x_minus_1));
 
 	/* Compute CAS latencies below that defined by SPD */
-	pdimm->caslat_lowest_derated
-		= compute_derated_DDR2_CAS_latency(get_memory_clk_period_ps());
+	pdimm->caslat_lowest_derated = compute_derated_DDR2_CAS_latency(
+					get_memory_clk_period_ps(ctrl_num));
 
 	/* Compute timing parameters */
 	pdimm->trcd_ps = spd->trcd * 250;
diff --git a/drivers/ddr/fsl/ddr3_dimm_params.c b/drivers/ddr/fsl/ddr3_dimm_params.c
index a4b8c10..6917715 100644
--- a/drivers/ddr/fsl/ddr3_dimm_params.c
+++ b/drivers/ddr/fsl/ddr3_dimm_params.c
@@ -83,10 +83,10 @@ compute_ranksize(const ddr3_spd_eeprom_t *spd)
  * Writes the results to the dimm_params_t structure pointed by pdimm.
  *
  */
-unsigned int
-ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
-			     dimm_params_t *pdimm,
-			     unsigned int dimm_number)
+unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
+					 const ddr3_spd_eeprom_t *spd,
+					 dimm_params_t *pdimm,
+					 unsigned int dimm_number)
 {
 	unsigned int retval;
 	unsigned int mtb_ps;
diff --git a/drivers/ddr/fsl/ddr4_dimm_params.c b/drivers/ddr/fsl/ddr4_dimm_params.c
index aaddc8f..bbfb4ee 100644
--- a/drivers/ddr/fsl/ddr4_dimm_params.c
+++ b/drivers/ddr/fsl/ddr4_dimm_params.c
@@ -119,10 +119,10 @@ compute_ranksize(const struct ddr4_spd_eeprom_s *spd)
  * Writes the results to the dimm_params_t structure pointed by pdimm.
  *
  */
-unsigned int
-ddr_compute_dimm_parameters(const generic_spd_eeprom_t *spd,
-			    dimm_params_t *pdimm,
-			    unsigned int dimm_number)
+unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
+					 const generic_spd_eeprom_t *spd,
+					 dimm_params_t *pdimm,
+					 unsigned int dimm_number)
 {
 	unsigned int retval;
 	int i;
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 4eef047..d9fce7d 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -32,24 +32,44 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	u32 temp_sdram_cfg;
 	u32 total_gb_size_per_controller;
 	int timeout;
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
+	defined(CONFIG_SYS_FSL_ERRATUM_A008514)
+	u32 *eddrtqcr1;
+#endif
 
 	switch (ctrl_num) {
 	case 0:
 		ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
+	defined(CONFIG_SYS_FSL_ERRATUM_A008514)
+		eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
+#endif
 		break;
 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
 	case 1:
 		ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
+	defined(CONFIG_SYS_FSL_ERRATUM_A008514)
+		eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
+#endif
 		break;
 #endif
 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
 	case 2:
 		ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
+	defined(CONFIG_SYS_FSL_ERRATUM_A008514)
+		eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
+#endif
 		break;
 #endif
 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
 	case 3:
 		ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
+	defined(CONFIG_SYS_FSL_ERRATUM_A008514)
+		eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR4_ADDR + 0x800;
+#endif
 		break;
 #endif
 	default:
@@ -60,6 +80,20 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	if (step == 2)
 		goto step2;
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
+#ifdef CONFIG_LS2085A
+	/* A008336 only applies to general DDR controllers */
+	if ((ctrl_num == 0) || (ctrl_num == 1))
+#endif
+		ddr_out32(eddrtqcr1, 0x63b30002);
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
+#ifdef CONFIG_LS2085A
+	/* A008514 only applies to DP-DDR controler */
+	if (ctrl_num == 2)
+#endif
+		ddr_out32(eddrtqcr1, 0x63b20002);
+#endif
 	if (regs->ddr_eor)
 		ddr_out32(&ddr->eor, regs->ddr_eor);
 
@@ -253,7 +287,7 @@ step2:
 	bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
 			>> SDRAM_CFG_DBW_SHIFT);
 	timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
-		(get_ddr_freq(0) >> 20)) << 2;
+		(get_ddr_freq(ctrl_num) >> 20)) << 2;
 	total_gb_size_per_controller >>= 4;	/* shift down to gb size */
 	debug("total %d GB\n", total_gb_size_per_controller);
 	debug("Need to wait up to %d * 10ms\n", timeout);
diff --git a/drivers/ddr/fsl/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c
index 73db444..b295344 100644
--- a/drivers/ddr/fsl/lc_common_dimm_params.c
+++ b/drivers/ddr/fsl/lc_common_dimm_params.c
@@ -13,7 +13,8 @@
 
 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 static unsigned int
-compute_cas_latency(const dimm_params_t *dimm_params,
+compute_cas_latency(const unsigned int ctrl_num,
+		    const dimm_params_t *dimm_params,
 		    common_timing_params_t *outpdimm,
 		    unsigned int number_of_dimms)
 {
@@ -22,7 +23,7 @@ compute_cas_latency(const dimm_params_t *dimm_params,
 	unsigned int caslat_actual;
 	unsigned int retry = 16;
 	unsigned int tmp;
-	const unsigned int mclk_ps = get_memory_clk_period_ps();
+	const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 #ifdef CONFIG_SYS_FSL_DDR3
 	const unsigned int taamax = 20000;
 #else
@@ -72,12 +73,13 @@ compute_cas_latency(const dimm_params_t *dimm_params,
 }
 #else	/* for DDR1 and DDR2 */
 static unsigned int
-compute_cas_latency(const dimm_params_t *dimm_params,
+compute_cas_latency(const unsigned int ctrl_num,
+		    const dimm_params_t *dimm_params,
 		    common_timing_params_t *outpdimm,
 		    unsigned int number_of_dimms)
 {
 	int i;
-	const unsigned int mclk_ps = get_memory_clk_period_ps();
+	const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 	unsigned int lowest_good_caslat;
 	unsigned int not_ok;
 	unsigned int temp1, temp2;
@@ -212,7 +214,8 @@ compute_cas_latency(const dimm_params_t *dimm_params,
  * by dimm_params.
  */
 unsigned int
-compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
+compute_lowest_common_dimm_parameters(const unsigned int ctrl_num,
+				      const dimm_params_t *dimm_params,
 				      common_timing_params_t *outpdimm,
 				      const unsigned int number_of_dimms)
 {
@@ -442,7 +445,8 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 		printf("ERROR: Mix different RDIMM detected!\n");
 
 	/* calculate cas latency for all DDR types */
-	if (compute_cas_latency(dimm_params, outpdimm, number_of_dimms))
+	if (compute_cas_latency(ctrl_num, dimm_params,
+				outpdimm, number_of_dimms))
 		return 1;
 
 	/* Determine if all DIMMs ECC capable. */
@@ -518,11 +522,12 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 
 #if defined(CONFIG_SYS_FSL_DDR2)
 	if ((outpdimm->lowest_common_spd_caslat < 4) &&
-	    (picos_to_mclk(trcd_ps) > outpdimm->lowest_common_spd_caslat)) {
-		additive_latency = picos_to_mclk(trcd_ps) -
+	    (picos_to_mclk(ctrl_num, trcd_ps) >
+	     outpdimm->lowest_common_spd_caslat)) {
+		additive_latency = picos_to_mclk(ctrl_num, trcd_ps) -
 				   outpdimm->lowest_common_spd_caslat;
-		if (mclk_to_picos(additive_latency) > trcd_ps) {
-			additive_latency = picos_to_mclk(trcd_ps);
+		if (mclk_to_picos(ctrl_num, additive_latency) > trcd_ps) {
+			additive_latency = picos_to_mclk(ctrl_num, trcd_ps);
 			debug("setting additive_latency to %u because it was "
 				" greater than tRCD_ps\n", additive_latency);
 		}
@@ -534,7 +539,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 	 *
 	 * AL <= tRCD(min)
 	 */
-	if (mclk_to_picos(additive_latency) > trcd_ps) {
+	if (mclk_to_picos(ctrl_num, additive_latency) > trcd_ps) {
 		printf("Error: invalid additive latency exceeds tRCD(min).\n");
 		return 1;
 	}
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index 6f291eb..b72b242 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -450,7 +450,8 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 					&(pinfo->spd_installed_dimms[i][j]);
 				dimm_params_t *pdimm =
 					&(pinfo->dimm_params[i][j]);
-				retval = compute_dimm_parameters(spd, pdimm, i);
+				retval = compute_dimm_parameters(
+							i, spd, pdimm, j);
 #ifdef CONFIG_SYS_DDR_RAW_TIMING
 				if (!i && !j && retval) {
 					printf("SPD error on controller %d! "
@@ -507,10 +508,11 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 		for (i = first_ctrl; i <= last_ctrl; i++) {
 			debug("Computing lowest common DIMM"
 				" parameters for memctl=%u\n", i);
-			compute_lowest_common_dimm_parameters(
-				pinfo->dimm_params[i],
-				&timing_params[i],
-				CONFIG_DIMM_SLOTS_PER_CTLR);
+			compute_lowest_common_dimm_parameters
+				(i,
+				 pinfo->dimm_params[i],
+				 &timing_params[i],
+				 CONFIG_DIMM_SLOTS_PER_CTLR);
 		}
 
 	case STEP_GATHER_OPTS:
@@ -562,12 +564,13 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 				continue;
 			}
 
-			compute_fsl_memctl_config_regs(
-					&pinfo->memctl_opts[i],
-					&ddr_reg[i], &timing_params[i],
-					pinfo->dimm_params[i],
-					dbw_capacity_adjust[i],
-					size_only);
+			compute_fsl_memctl_config_regs
+				(i,
+				 &pinfo->memctl_opts[i],
+				 &ddr_reg[i], &timing_params[i],
+				 pinfo->dimm_params[i],
+				 dbw_capacity_adjust[i],
+				 size_only);
 		}
 
 	default:
@@ -689,6 +692,10 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
 		}
 	}
 
+#ifdef CONFIG_FSL_DDR_SYNC_REFRESH
+	fsl_ddr_sync_memctl_refresh(first_ctrl, last_ctrl);
+#endif
+
 #ifdef CONFIG_PPC
 	/* program LAWs */
 	for (i = first_ctrl; i <= last_ctrl; i++) {
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
index 8f4d01a..6752d4d 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
@@ -426,7 +426,7 @@ step2:
 	bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
 			>> SDRAM_CFG_DBW_SHIFT);
 	timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
-		(get_ddr_freq(0) >> 20)) << 1;
+		(get_ddr_freq(ctrl_num) >> 20)) << 1;
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 	timeout_save = timeout;
 #endif
@@ -538,12 +538,14 @@ step2:
 		case 1:
 			out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);
 			break;
+#if CONFIG_CHIP_SELECTS_PER_CTRL > 2
 		case 2:
 			out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);
 			break;
 		case 3:
 			out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);
 			break;
+#endif
 		}
 		clrbits_be32(&ddr->sdram_cfg, 0x2);
 	}
diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c
index 6d098d1..5beb11b 100644
--- a/drivers/ddr/fsl/options.c
+++ b/drivers/ddr/fsl/options.c
@@ -732,7 +732,7 @@ unsigned int populate_memctl_options(int all_dimms_registered,
 #endif
 
 	/* Global Timing Parameters. */
-	debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
+	debug("mclk_ps = %u ps\n", get_memory_clk_period_ps(ctrl_num));
 
 	/* Pick a caslat override. */
 	popts->cas_latency_override = 0;
@@ -785,7 +785,7 @@ unsigned int populate_memctl_options(int all_dimms_registered,
 	 * FIXME: width, was considering looking at pdimm->primary_sdram_width
 	 */
 #if defined(CONFIG_SYS_FSL_DDR1)
-	popts->tfaw_window_four_activates_ps = mclk_to_picos(1);
+	popts->tfaw_window_four_activates_ps = mclk_to_picos(ctrl_num, 1);
 
 #elif defined(CONFIG_SYS_FSL_DDR2)
 	/*
@@ -1036,7 +1036,7 @@ done:
 	if (pdimm[0].n_ranks == 4)
 		popts->quad_rank_present = 1;
 
-	ddr_freq = get_ddr_freq(0) / 1000000;
+	ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
 	if (popts->registered_dimm_en) {
 		popts->rcw_override = 1;
 		popts->rcw_1 = 0x000a5a00;
diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c
index 58b519b..664081b 100644
--- a/drivers/ddr/fsl/util.c
+++ b/drivers/ddr/fsl/util.c
@@ -43,9 +43,9 @@ u32 fsl_ddr_get_version(void)
  * propagation, compute a suitably rounded mclk_ps to compute
  * a working memory controller configuration.
  */
-unsigned int get_memory_clk_period_ps(void)
+unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num)
 {
-	unsigned int data_rate = get_ddr_freq(0);
+	unsigned int data_rate = get_ddr_freq(ctrl_num);
 	unsigned int result;
 
 	/* Round to nearest 10ps, being careful about 64-bit multiply/divide */
@@ -59,10 +59,10 @@ unsigned int get_memory_clk_period_ps(void)
 }
 
 /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
-unsigned int picos_to_mclk(unsigned int picos)
+unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos)
 {
 	unsigned long long clks, clks_rem;
-	unsigned long data_rate = get_ddr_freq(0);
+	unsigned long data_rate = get_ddr_freq(ctrl_num);
 
 	/* Short circuit for zero picos */
 	if (!picos)
@@ -88,9 +88,9 @@ unsigned int picos_to_mclk(unsigned int picos)
 	return (unsigned int) clks;
 }
 
-unsigned int mclk_to_picos(unsigned int mclk)
+unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk)
 {
-	return get_memory_clk_period_ps() * mclk;
+	return get_memory_clk_period_ps(ctrl_num) * mclk;
 }
 
 #ifdef CONFIG_PPC
@@ -308,3 +308,58 @@ void board_add_ram_info(int use_default)
 {
 	detail_board_ddr_info();
 }
+
+#ifdef CONFIG_FSL_DDR_SYNC_REFRESH
+#define DDRC_DEBUG20_INIT_DONE	0x80000000
+#define DDRC_DEBUG2_RF		0x00000040
+void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
+				 unsigned int last_ctrl)
+{
+	unsigned int i;
+	u32 ddrc_debug20;
+	u32 ddrc_debug2[CONFIG_NUM_DDR_CONTROLLERS] = {};
+	u32 *ddrc_debug2_p[CONFIG_NUM_DDR_CONTROLLERS] = {};
+	struct ccsr_ddr __iomem *ddr;
+
+	for (i = first_ctrl; i <= last_ctrl; i++) {
+		switch (i) {
+		case 0:
+			ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+			break;
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+		case 1:
+			ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+			break;
+#endif
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+		case 2:
+			ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+			break;
+#endif
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+		case 3:
+			ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
+			break;
+#endif
+		default:
+			printf("%s unexpected ctrl = %u\n", __func__, i);
+			return;
+		}
+		ddrc_debug20 = ddr_in32(&ddr->debug[19]);
+		ddrc_debug2_p[i] = &ddr->debug[1];
+		while (!(ddrc_debug20 & DDRC_DEBUG20_INIT_DONE)) {
+			/* keep polling until DDRC init is done */
+			udelay(100);
+			ddrc_debug20 = ddr_in32(&ddr->debug[19]);
+		}
+		ddrc_debug2[i] = ddr_in32(&ddr->debug[1]) | DDRC_DEBUG2_RF;
+	}
+	/*
+	 * Sync refresh
+	 * This is put together to make sure the refresh reqeusts are sent
+	 * closely to each other.
+	 */
+	for (i = first_ctrl; i <= last_ctrl; i++)
+		ddr_out32(ddrc_debug2_p[i], ddrc_debug2[i]);
+}
+#endif /* CONFIG_FSL_DDR_SYNC_REFRESH */
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index c55eb28..f5d2ccb 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -319,7 +319,8 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 	esdhc_write32(&regs->cmdarg, cmd->cmdarg);
 #if defined(CONFIG_FSL_USDHC)
 	esdhc_write32(&regs->mixctrl,
-	(esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F));
+	(esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
+			| (mmc->ddr_mode ? XFERTYP_DDREN : 0));
 	esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
 #else
 	esdhc_write32(&regs->xfertyp, xfertyp);
@@ -442,7 +443,7 @@ static void set_sysctl(struct mmc *mmc, uint clock)
 		if ((sdhc_clk / (div * pre_div)) <= clock)
 			break;
 
-	pre_div >>= 1;
+	pre_div >>= mmc->ddr_mode ? 2 : 1;
 	div -= 1;
 
 	clk = (pre_div << 8) | (div << 4);
@@ -601,6 +602,9 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 	}
 
 	cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
+#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
+	cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz;
+#endif
 
 	if (cfg->max_bus_width > 0) {
 		if (cfg->max_bus_width < 8)
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index da5e2bc..b8b0803 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -64,5 +64,5 @@ obj-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
 obj-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \
 		xilinx_ll_temac_fifo.o xilinx_ll_temac_sdma.o
 obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o
-obj-$(CONFIG_FSL_MC_ENET) += fsl_mc/
+obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/
 obj-$(CONFIG_VSC9953) += vsc9953.o
diff --git a/drivers/net/fsl_mc/Makefile b/drivers/net/fsl-mc/Makefile
index 4834086..206ac6b 100644
--- a/drivers/net/fsl_mc/Makefile
+++ b/drivers/net/fsl-mc/Makefile
@@ -5,4 +5,6 @@
 #
 
 # Layerscape MC driver
-obj-y += mc.o
+obj-y += mc.o \
+	mc_sys.o \
+	dpmng.o
diff --git a/drivers/net/fsl-mc/dpmng.c b/drivers/net/fsl-mc/dpmng.c
new file mode 100644
index 0000000..cc14c7b
--- /dev/null
+++ b/drivers/net/fsl-mc/dpmng.c
@@ -0,0 +1,91 @@
+/* Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <fsl-mc/fsl_mc_sys.h>
+#include <fsl-mc/fsl_mc_cmd.h>
+#include <fsl-mc/fsl_dpmng.h>
+#include "fsl_dpmng_cmd.h"
+
+int mc_get_version(struct fsl_mc_io *mc_io, struct mc_version *mc_ver_info)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPMNG_CMDID_GET_VERSION,
+					  MC_CMD_PRI_LOW, 0);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	DPMNG_RSP_GET_VERSION(cmd, mc_ver_info);
+
+	return 0;
+}
+
+int dpmng_reset_aiop(struct fsl_mc_io *mc_io, int container_id,
+		     int aiop_tile_id)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPMNG_CMDID_RESET_AIOP,
+					  MC_CMD_PRI_LOW, 0);
+	DPMNG_CMD_RESET_AIOP(cmd, container_id, aiop_tile_id);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpmng_load_aiop(struct fsl_mc_io *mc_io,
+		    int container_id,
+		    int aiop_tile_id,
+		    uint64_t img_iova,
+		    uint32_t img_size)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPMNG_CMDID_LOAD_AIOP,
+					  MC_CMD_PRI_LOW,
+					  0);
+	DPMNG_CMD_LOAD_AIOP(cmd, container_id, aiop_tile_id, img_size,
+			    img_iova);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpmng_run_aiop(struct fsl_mc_io *mc_io,
+		   int container_id,
+		   int aiop_tile_id,
+		   const struct dpmng_aiop_run_cfg *cfg)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPMNG_CMDID_RUN_AIOP,
+					  MC_CMD_PRI_LOW,
+					  0);
+	DPMNG_CMD_RUN_AIOP(cmd, container_id, aiop_tile_id, cfg);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpmng_reset_mc_portal(struct fsl_mc_io *mc_io)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPMNG_CMDID_RESET_MC_PORTAL,
+					  MC_CMD_PRI_LOW,
+					  0);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
diff --git a/drivers/net/fsl-mc/fsl_dpmng_cmd.h b/drivers/net/fsl-mc/fsl_dpmng_cmd.h
new file mode 100644
index 0000000..c9fe021
--- /dev/null
+++ b/drivers/net/fsl-mc/fsl_dpmng_cmd.h
@@ -0,0 +1,49 @@
+/* Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __FSL_DPMNG_CMD_H
+#define __FSL_DPMNG_CMD_H
+
+/* Command IDs */
+#define DPMNG_CMDID_GET_VERSION			0x831
+#define DPMNG_CMDID_RESET_AIOP			0x832
+#define DPMNG_CMDID_LOAD_AIOP			0x833
+#define DPMNG_CMDID_RUN_AIOP			0x834
+#define DPMNG_CMDID_RESET_MC_PORTAL		0x835
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPMNG_RSP_GET_VERSION(cmd, mc_ver_info) \
+do { \
+	MC_RSP_OP(cmd, 0, 0,  32, uint32_t, mc_ver_info->revision); \
+	MC_RSP_OP(cmd, 0, 32, 32, uint32_t, mc_ver_info->major); \
+	MC_RSP_OP(cmd, 1, 0,  32, uint32_t, mc_ver_info->minor); \
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPMNG_CMD_RESET_AIOP(cmd, container_id, aiop_tile_id) \
+do { \
+	MC_CMD_OP(cmd, 0, 0,  32, int,      aiop_tile_id); \
+	MC_CMD_OP(cmd, 0, 32, 32, int,      container_id); \
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPMNG_CMD_LOAD_AIOP(cmd, container_id, aiop_tile_id, img_size, \
+			    img_iova) \
+do { \
+	MC_CMD_OP(cmd, 0, 0,  32, int,      aiop_tile_id); \
+	MC_CMD_OP(cmd, 0, 32, 32, int,      container_id); \
+	MC_CMD_OP(cmd, 1, 0,  32, uint32_t, img_size); \
+	MC_CMD_OP(cmd, 2, 0,  64, uint64_t, img_iova); \
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPMNG_CMD_RUN_AIOP(cmd, container_id, aiop_tile_id, cfg) \
+do { \
+	MC_CMD_OP(cmd, 0, 0,  32, int,	    aiop_tile_id); \
+	MC_CMD_OP(cmd, 0, 32, 32, int,      container_id); \
+	MC_CMD_OP(cmd, 1, 0,  32, uint32_t, cfg->cores_mask); \
+	MC_CMD_OP(cmd, 2, 0,  64, uint64_t, cfg->options); \
+} while (0)
+
+#endif /* __FSL_DPMNG_CMD_H */
diff --git a/drivers/net/fsl_mc/mc.c b/drivers/net/fsl-mc/mc.c
index df84568..74b0085 100644
--- a/drivers/net/fsl_mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -3,9 +3,12 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
+
 #include <errno.h>
 #include <asm/io.h>
-#include <fsl_mc.h>
+#include <fsl-mc/fsl_mc.h>
+#include <fsl-mc/fsl_mc_sys.h>
+#include <fsl-mc/fsl_dpmng.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 static int mc_boot_status;
@@ -14,7 +17,7 @@ static int mc_boot_status;
  * Copying MC firmware or DPL image to DDR
  */
 static int mc_copy_image(const char *title,
-		    u64 image_addr, u32 image_size, u64 mc_ram_addr)
+			 u64 image_addr, u32 image_size, u64 mc_ram_addr)
 {
 	debug("%s copied to address %p\n", title, (void *)mc_ram_addr);
 	memcpy((void *)mc_ram_addr, (void *)image_addr, image_size);
@@ -25,10 +28,9 @@ static int mc_copy_image(const char *title,
  * MC firmware FIT image parser checks if the image is in FIT
  * format, verifies integrity of the image and calculates
  * raw image address and size values.
- * Returns 0 if success and 1 if any of the above mentioned
+ * Returns 0 on success and a negative errno on error.
  * task fail.
  **/
-
 int parse_mc_firmware_fit_image(const void **raw_image_addr,
 				size_t *raw_image_size)
 {
@@ -39,7 +41,7 @@ int parse_mc_firmware_fit_image(const void **raw_image_addr,
 	size_t size;
 	const char *uname = "firmware";
 
-	/* Check if the image is in NOR flash*/
+	/* Check if the image is in NOR flash */
 #ifdef CONFIG_SYS_LS_MC_FW_IN_NOR
 	fit_hdr = (void *)CONFIG_SYS_LS_MC_FW_ADDR;
 #else
@@ -50,26 +52,26 @@ int parse_mc_firmware_fit_image(const void **raw_image_addr,
 	format = genimg_get_format(fit_hdr);
 
 	if (format != IMAGE_FORMAT_FIT) {
-		debug("Not a FIT image\n");
-		return 1;
+		printf("fsl-mc: ERROR: Bad firmware image (not a FIT image)\n");
+		return -EINVAL;
 	}
 
 	if (!fit_check_format(fit_hdr)) {
-		debug("Bad FIT image format\n");
-		return 1;
+		printf("fsl-mc: ERROR: Bad firmware image (bad FIT header)\n");
+		return -EINVAL;
 	}
 
 	node_offset = fit_image_get_node(fit_hdr, uname);
 
 	if (node_offset < 0) {
-		debug("Can not find %s subimage\n", uname);
-		return 1;
+		printf("fsl-mc: ERROR: Bad firmware image (missing subimage)\n");
+		return -ENOENT;
 	}
 
 	/* Verify MC firmware image */
 	if (!(fit_image_verify(fit_hdr, node_offset))) {
-		debug("Bad MC firmware hash");
-		return 1;
+		printf("fsl-mc: ERROR: Bad firmware image (bad CRC)\n");
+		return -EINVAL;
 	}
 
 	/* Get address and size of raw image */
@@ -90,12 +92,13 @@ int mc_init(bd_t *bis)
 	u64 mc_dpl_offset;
 	u32 reg_gsr;
 	u32 mc_fw_boot_status;
-	void *fdt_hdr;
+	void *dpl_fdt_hdr;
 	int dpl_size;
 	const void *raw_image_addr;
 	size_t raw_image_size = 0;
-
-	BUILD_BUG_ON(CONFIG_SYS_LS_MC_FW_LENGTH % 4 != 0);
+	struct fsl_mc_io mc_io;
+	int portal_id;
+	struct mc_version mc_ver_info;
 
 	/*
 	 * The MC private DRAM block was already carved at the end of DRAM
@@ -130,25 +133,44 @@ int mc_init(bd_t *bis)
 	/*
 	 * Load the MC FW at the beginning of the MC private DRAM block:
 	 */
-	mc_copy_image(
-		"MC Firmware",
-		(u64)raw_image_addr,
-		raw_image_size,
-		mc_ram_addr);
+	mc_copy_image("MC Firmware",
+		      (u64)raw_image_addr, raw_image_size, mc_ram_addr);
+
+	/*
+	 * Get address and size of the DPL blob stored in flash:
+	 */
+#ifdef CONFIG_SYS_LS_MC_DPL_IN_NOR
+	dpl_fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPL_ADDR;
+#else
+#error "No CONFIG_SYS_LS_MC_DPL_IN_xxx defined"
+#endif
+
+	error = fdt_check_header(dpl_fdt_hdr);
+	if (error != 0) {
+		printf("fsl-mc: ERROR: Bad DPL image (bad header)\n");
+		goto out;
+	}
+
+	dpl_size = fdt_totalsize(dpl_fdt_hdr);
+	if (dpl_size > CONFIG_SYS_LS_MC_DPL_MAX_LENGTH) {
+		printf("fsl-mc: ERROR: Bad DPL image (too large: %d)\n",
+		       dpl_size);
+		error = -EINVAL;
+		goto out;
+	}
 
 	/*
 	 * Calculate offset in the MC private DRAM block at which the MC DPL
 	 * blob is to be placed:
 	 */
 #ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
-	BUILD_BUG_ON(
-		(CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 ||
-		CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff);
+	BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 ||
+		     CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff);
 
 	mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET;
 #else
 	mc_dpl_offset = mc_get_dram_block_size() -
-			roundup(CONFIG_SYS_LS_MC_DPL_LENGTH, 4096);
+			roundup(CONFIG_SYS_LS_MC_DPL_MAX_LENGTH, 4096);
 
 	if ((mc_dpl_offset & 0x3) != 0 || mc_dpl_offset > 0xffffffff) {
 		printf("%s: Invalid MC DPL offset: %llu\n",
@@ -158,23 +180,14 @@ int mc_init(bd_t *bis)
 	}
 #endif
 
-	/* Check if DPL image is in NOR flash */
-#ifdef CONFIG_SYS_LS_MC_DPL_IN_NOR
-	fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPL_ADDR;
-#else
-#error "No CONFIG_SYS_LS_MC_DPL_IN_xxx defined"
-#endif
-
-	dpl_size = fdt_totalsize(fdt_hdr);
-
 	/*
 	 * Load the MC DPL blob at the far end of the MC private DRAM block:
+	 *
+	 * TODO: Should we place the DPL at a different location to match
+	 * assumptions of MC firmware about its memory layout?
 	 */
-	mc_copy_image(
-		"MC DPL blob",
-		(u64)fdt_hdr,
-		dpl_size,
-		mc_ram_addr + mc_dpl_offset);
+	mc_copy_image("MC DPL blob",
+		      (u64)dpl_fdt_hdr, dpl_size, mc_ram_addr + mc_dpl_offset);
 
 	debug("mc_ccsr_regs %p\n", mc_ccsr_regs);
 
@@ -200,6 +213,8 @@ int mc_init(bd_t *bis)
 	 */
 	out_le32(&mc_ccsr_regs->reg_gsr, (u32)(mc_dpl_offset >> 2));
 
+	printf("\nfsl-mc: Booting Management Complex ...\n");
+
 	/*
 	 * Deassert reset and release MC core 0 to run
 	 */
@@ -219,17 +234,13 @@ int mc_init(bd_t *bis)
 	}
 
 	if (timeout <= 0) {
-		printf("%s: timeout booting management complex firmware\n",
-		       __func__);
+		printf("fsl-mc: timeout booting management complex firmware\n");
 
 		/* TODO: Get an error status from an MC CCSR register */
 		error = -ETIMEDOUT;
 		goto out;
 	}
 
-	printf("Management complex booted (boot status: %#x)\n",
-	       mc_fw_boot_status);
-
 	if (mc_fw_boot_status != 0x1) {
 		/*
 		 * TODO: Identify critical errors from the GSR register's FS
@@ -237,8 +248,41 @@ int mc_init(bd_t *bis)
 		 * appropriate errno, so that the status property is set to
 		 * failure in the fsl,dprc device tree node.
 		 */
+		printf("fsl-mc: WARNING: Firmware booted with error (GSR: %#x)\n",
+		       reg_gsr);
 	}
 
+	/*
+	 * TODO: need to obtain the portal_id for the root container from the
+	 * DPL
+	 */
+	portal_id = 0;
+
+	/*
+	 * Check that the MC firmware is responding portal commands:
+	 */
+	mc_io.mmio_regs = SOC_MC_PORTAL_ADDR(portal_id);
+	debug("Checking access to MC portal of root DPRC container (portal_id %d, portal physical addr %p)\n",
+	      portal_id, mc_io.mmio_regs);
+
+	error = mc_get_version(&mc_io, &mc_ver_info);
+	if (error != 0) {
+		printf("fsl-mc: ERROR: Firmware version check failed (error: %d)\n",
+		       error);
+		goto out;
+	}
+
+	if (MC_VER_MAJOR != mc_ver_info.major)
+		printf("fsl-mc: ERROR: Firmware major version mismatch (found: %d, expected: %d)\n",
+		       mc_ver_info.major, MC_VER_MAJOR);
+
+	if (MC_VER_MINOR != mc_ver_info.minor)
+		printf("fsl-mc: WARNING: Firmware minor version mismatch (found: %d, expected: %d)\n",
+		       mc_ver_info.minor, MC_VER_MINOR);
+
+	printf("fsl-mc: Management Complex booted (version: %d.%d.%d, boot status: %#x)\n",
+	       mc_ver_info.major, mc_ver_info.minor, mc_ver_info.revision,
+	       mc_fw_boot_status);
 out:
 	if (error != 0)
 		mc_boot_status = -error;
diff --git a/drivers/net/fsl-mc/mc_sys.c b/drivers/net/fsl-mc/mc_sys.c
new file mode 100644
index 0000000..7c8e003
--- /dev/null
+++ b/drivers/net/fsl-mc/mc_sys.c
@@ -0,0 +1,63 @@
+/*
+ * Freescale Layerscape MC I/O wrapper
+ *
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ * Author: German Rivera <German.Rivera@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <fsl-mc/fsl_mc_sys.h>
+#include <fsl-mc/fsl_mc_cmd.h>
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+
+#define MC_CMD_HDR_READ_CMDID(_hdr) \
+	((uint16_t)u64_dec((_hdr), MC_CMD_HDR_CMDID_O, MC_CMD_HDR_CMDID_S))
+
+/**
+ * mc_send_command - Send MC command and wait for response
+ *
+ * @mc_io: Pointer to MC I/O object to be used
+ * @cmd: MC command buffer. On input, it contains the command to send to the MC.
+ * On output, it contains the response from the MC if any.
+ *
+ * Depending on the sharing option specified when creating the MC portal
+ * wrapper, this function will use a spinlock or mutex to ensure exclusive
+ * access to the MC portal from the point when the command is sent until a
+ * response is received from the MC.
+ */
+int mc_send_command(struct fsl_mc_io *mc_io,
+		    struct mc_command *cmd)
+{
+	enum mc_cmd_status status;
+	int timeout = 2000;
+
+	mc_write_command(mc_io->mmio_regs, cmd);
+
+	for ( ; ; ) {
+		status = mc_read_response(mc_io->mmio_regs, cmd);
+		if (status != MC_CMD_STATUS_READY)
+			break;
+
+		if (--timeout == 0) {
+			printf("Error: Timeout waiting for MC response\n");
+			return -ETIMEDOUT;
+		}
+
+		udelay(500);
+	}
+
+	if (status != MC_CMD_STATUS_OK) {
+		printf("Error: MC command failed (portal: %p, obj handle: %#x, command: %#x, status: %#x)\n",
+		       mc_io->mmio_regs,
+		       (unsigned int)MC_CMD_HDR_READ_AUTHID(cmd->header),
+		       (unsigned int)MC_CMD_HDR_READ_CMDID(cmd->header),
+		       (unsigned int)status);
+
+		return -EIO;
+	}
+
+	return 0;
+}
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 291c249..bcad8f2 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
  * Layerscape PCIe driver
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -9,8 +9,465 @@
 #include <asm/arch/fsl_serdes.h>
 #include <pci.h>
 #include <asm/io.h>
+#include <errno.h>
+#include <malloc.h>
 #include <asm/pcie_layerscape.h>
 
+#ifndef CONFIG_SYS_PCI_MEMORY_BUS
+#define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
+#endif
+
+#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
+#define CONFIG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE
+#endif
+
+#ifndef CONFIG_SYS_PCI_MEMORY_SIZE
+#define CONFIG_SYS_PCI_MEMORY_SIZE (2 * 1024 * 1024 * 1024UL) /* 2G */
+#endif
+
+/* iATU registers */
+#define PCIE_ATU_VIEWPORT		0x900
+#define PCIE_ATU_REGION_INBOUND		(0x1 << 31)
+#define PCIE_ATU_REGION_OUTBOUND	(0x0 << 31)
+#define PCIE_ATU_REGION_INDEX0		(0x0 << 0)
+#define PCIE_ATU_REGION_INDEX1		(0x1 << 0)
+#define PCIE_ATU_REGION_INDEX2		(0x2 << 0)
+#define PCIE_ATU_REGION_INDEX3		(0x3 << 0)
+#define PCIE_ATU_CR1			0x904
+#define PCIE_ATU_TYPE_MEM		(0x0 << 0)
+#define PCIE_ATU_TYPE_IO		(0x2 << 0)
+#define PCIE_ATU_TYPE_CFG0		(0x4 << 0)
+#define PCIE_ATU_TYPE_CFG1		(0x5 << 0)
+#define PCIE_ATU_CR2			0x908
+#define PCIE_ATU_ENABLE			(0x1 << 31)
+#define PCIE_ATU_BAR_MODE_ENABLE	(0x1 << 30)
+#define PCIE_ATU_LOWER_BASE		0x90C
+#define PCIE_ATU_UPPER_BASE		0x910
+#define PCIE_ATU_LIMIT			0x914
+#define PCIE_ATU_LOWER_TARGET		0x918
+#define PCIE_ATU_BUS(x)			(((x) & 0xff) << 24)
+#define PCIE_ATU_DEV(x)			(((x) & 0x1f) << 19)
+#define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)
+#define PCIE_ATU_UPPER_TARGET		0x91C
+
+#define PCIE_LINK_CAP		0x7c
+#define PCIE_LINK_SPEED_MASK	0xf
+#define PCIE_LINK_STA		0x82
+
+#define PCIE_DBI_SIZE		(4 * 1024) /* 4K */
+
+struct ls_pcie {
+	int idx;
+	void __iomem *dbi;
+	void __iomem *va_cfg0;
+	void __iomem *va_cfg1;
+	struct pci_controller hose;
+};
+
+struct ls_pcie_info {
+	unsigned long regs;
+	int pci_num;
+	u64 cfg0_phys;
+	u64 cfg0_size;
+	u64 cfg1_phys;
+	u64 cfg1_size;
+	u64 mem_bus;
+	u64 mem_phys;
+	u64 mem_size;
+	u64 io_bus;
+	u64 io_phys;
+	u64 io_size;
+};
+
+#define SET_LS_PCIE_INFO(x, num)			\
+{							\
+	x.regs = CONFIG_SYS_PCIE##num##_ADDR;		\
+	x.cfg0_phys = CONFIG_SYS_PCIE_CFG0_PHYS_OFF +	\
+		      CONFIG_SYS_PCIE##num##_PHYS_ADDR;	\
+	x.cfg0_size = CONFIG_SYS_PCIE_CFG0_SIZE;	\
+	x.cfg1_phys = CONFIG_SYS_PCIE_CFG1_PHYS_OFF +	\
+		      CONFIG_SYS_PCIE##num##_PHYS_ADDR;	\
+	x.cfg1_size = CONFIG_SYS_PCIE_CFG1_SIZE;	\
+	x.mem_bus = CONFIG_SYS_PCIE_MEM_BUS;		\
+	x.mem_phys = CONFIG_SYS_PCIE_MEM_PHYS_OFF +	\
+		     CONFIG_SYS_PCIE##num##_PHYS_ADDR;	\
+	x.mem_size = CONFIG_SYS_PCIE_MEM_SIZE;		\
+	x.io_bus = CONFIG_SYS_PCIE_IO_BUS;		\
+	x.io_phys = CONFIG_SYS_PCIE_IO_PHYS_OFF +	\
+		    CONFIG_SYS_PCIE##num##_PHYS_ADDR;	\
+	x.io_size = CONFIG_SYS_PCIE_IO_SIZE;		\
+	x.pci_num = num;				\
+}
+
+#ifdef CONFIG_LS102XA
+#include <asm/arch/immap_ls102xa.h>
+
+/* PEX1/2 Misc Ports Status Register */
+#define LTSSM_STATE_SHIFT	20
+#define LTSSM_STATE_MASK	0x3f
+#define LTSSM_PCIE_L0		0x11 /* L0 state */
+
+static int ls_pcie_link_state(struct ls_pcie *pcie)
+{
+	u32 state;
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+	state = in_be32(&scfg->pexmscportsr[pcie->idx]);
+	state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
+	if (state < LTSSM_PCIE_L0) {
+		debug("....PCIe link error. LTSSM=0x%02x.\n", state);
+		return 0;
+	}
+
+	return 1;
+}
+#else
+#define PCIE_LDBG 0x7FC
+
+static int ls_pcie_link_state(struct ls_pcie *pcie)
+{
+	u32 state;
+
+	state = readl(pcie->dbi + PCIE_LDBG);
+	if (state)
+		return 1;
+
+	debug("....PCIe link error.\n");
+	return 0;
+}
+#endif
+
+static int ls_pcie_link_up(struct ls_pcie *pcie)
+{
+	int state;
+	u32 cap;
+
+	state = ls_pcie_link_state(pcie);
+	if (state)
+		return state;
+
+	/* Try to download speed to gen1 */
+	cap = readl(pcie->dbi + PCIE_LINK_CAP);
+	writel((cap & (~PCIE_LINK_SPEED_MASK)) | 1, pcie->dbi + PCIE_LINK_CAP);
+	udelay(2000);
+	state = ls_pcie_link_state(pcie);
+	if (state)
+		return state;
+
+	writel(cap, pcie->dbi + PCIE_LINK_CAP);
+
+	return 0;
+}
+
+static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
+{
+	writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
+	       pcie->dbi + PCIE_ATU_VIEWPORT);
+	writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET);
+}
+
+static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev)
+{
+	writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
+	       pcie->dbi + PCIE_ATU_VIEWPORT);
+	writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET);
+}
+
+static void ls_pcie_iatu_outbound_set(struct ls_pcie *pcie, int idx, int type,
+				      u64 phys, u64 bus_addr, pci_size_t size)
+{
+	writel(PCIE_ATU_REGION_OUTBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT);
+	writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_BASE);
+	writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_BASE);
+	writel(phys + size - 1, pcie->dbi + PCIE_ATU_LIMIT);
+	writel((u32)bus_addr, pcie->dbi + PCIE_ATU_LOWER_TARGET);
+	writel(bus_addr >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET);
+	writel(type, pcie->dbi + PCIE_ATU_CR1);
+	writel(PCIE_ATU_ENABLE, pcie->dbi + PCIE_ATU_CR2);
+}
+
+static void ls_pcie_setup_atu(struct ls_pcie *pcie, struct ls_pcie_info *info)
+{
+#ifdef DEBUG
+	int i;
+#endif
+
+	/* ATU 0 : OUTBOUND : CFG0 */
+	ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
+				  PCIE_ATU_TYPE_CFG0,
+				  info->cfg0_phys,
+				  0,
+				  info->cfg0_size);
+	/* ATU 1 : OUTBOUND : CFG1 */
+	ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
+				  PCIE_ATU_TYPE_CFG1,
+				  info->cfg1_phys,
+				  0,
+				  info->cfg1_size);
+	/* ATU 2 : OUTBOUND : MEM */
+	ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX2,
+				  PCIE_ATU_TYPE_MEM,
+				  info->mem_phys,
+				  info->mem_bus,
+				  info->mem_size);
+	/* ATU 3 : OUTBOUND : IO */
+	ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX3,
+				  PCIE_ATU_TYPE_IO,
+				  info->io_phys,
+				  info->io_bus,
+				  info->io_size);
+
+#ifdef DEBUG
+	for (i = 0; i <= PCIE_ATU_REGION_INDEX3; i++) {
+		writel(PCIE_ATU_REGION_OUTBOUND | i,
+		       pcie->dbi + PCIE_ATU_VIEWPORT);
+		debug("iATU%d:\n", i);
+		debug("\tLOWER PHYS 0x%08x\n",
+		      readl(pcie->dbi + PCIE_ATU_LOWER_BASE));
+		debug("\tUPPER PHYS 0x%08x\n",
+		      readl(pcie->dbi + PCIE_ATU_UPPER_BASE));
+		debug("\tLOWER BUS  0x%08x\n",
+		      readl(pcie->dbi + PCIE_ATU_LOWER_TARGET));
+		debug("\tUPPER BUS  0x%08x\n",
+		      readl(pcie->dbi + PCIE_ATU_UPPER_TARGET));
+		debug("\tLIMIT      0x%08x\n",
+		      readl(pcie->dbi + PCIE_ATU_LIMIT));
+		debug("\tCR1        0x%08x\n",
+		      readl(pcie->dbi + PCIE_ATU_CR1));
+		debug("\tCR2        0x%08x\n",
+		      readl(pcie->dbi + PCIE_ATU_CR2));
+	}
+#endif
+}
+
+int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
+{
+	/* Do not skip controller */
+	return 0;
+}
+
+static int ls_pcie_addr_valid(struct pci_controller *hose, pci_dev_t d)
+{
+	if (PCI_DEV(d) > 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int ls_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
+			       int where, u32 *val)
+{
+	struct ls_pcie *pcie = hose->priv_data;
+	u32 busdev, *addr;
+
+	if (ls_pcie_addr_valid(hose, d)) {
+		*val = 0xffffffff;
+		return -EINVAL;
+	}
+
+	if (PCI_BUS(d) == hose->first_busno) {
+		addr = pcie->dbi + (where & ~0x3);
+	} else {
+		busdev = PCIE_ATU_BUS(PCI_BUS(d)) |
+			 PCIE_ATU_DEV(PCI_DEV(d)) |
+			 PCIE_ATU_FUNC(PCI_FUNC(d));
+
+		if (PCI_BUS(d) == hose->first_busno + 1) {
+			ls_pcie_cfg0_set_busdev(pcie, busdev);
+			addr = pcie->va_cfg0 + (where & ~0x3);
+		} else {
+			ls_pcie_cfg1_set_busdev(pcie, busdev);
+			addr = pcie->va_cfg1 + (where & ~0x3);
+		}
+	}
+
+	*val = readl(addr);
+
+	return 0;
+}
+
+static int ls_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
+				int where, u32 val)
+{
+	struct ls_pcie *pcie = hose->priv_data;
+	u32 busdev, *addr;
+
+	if (ls_pcie_addr_valid(hose, d))
+		return -EINVAL;
+
+	if (PCI_BUS(d) == hose->first_busno) {
+		addr = pcie->dbi + (where & ~0x3);
+	} else {
+		busdev = PCIE_ATU_BUS(PCI_BUS(d)) |
+			 PCIE_ATU_DEV(PCI_DEV(d)) |
+			 PCIE_ATU_FUNC(PCI_FUNC(d));
+
+		if (PCI_BUS(d) == hose->first_busno + 1) {
+			ls_pcie_cfg0_set_busdev(pcie, busdev);
+			addr = pcie->va_cfg0 + (where & ~0x3);
+		} else {
+			ls_pcie_cfg1_set_busdev(pcie, busdev);
+			addr = pcie->va_cfg1 + (where & ~0x3);
+		}
+	}
+
+	writel(val, addr);
+
+	return 0;
+}
+
+static void ls_pcie_setup_ctrl(struct ls_pcie *pcie,
+			       struct ls_pcie_info *info)
+{
+	struct pci_controller *hose = &pcie->hose;
+	pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
+
+	ls_pcie_setup_atu(pcie, info);
+
+	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0);
+
+	/* program correct class for RC */
+	pci_hose_write_config_word(hose, dev, PCI_CLASS_DEVICE,
+				   PCI_CLASS_BRIDGE_PCI);
+}
+
+int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info)
+{
+	struct ls_pcie *pcie;
+	struct pci_controller *hose;
+	int num = dev - PCIE1;
+	pci_dev_t pdev = PCI_BDF(busno, 0, 0);
+	int i, linkup, ep_mode;
+	u8 header_type;
+	u16 temp16;
+
+	if (!is_serdes_configured(dev)) {
+		printf("PCIe%d: disabled\n", num + 1);
+		return busno;
+	}
+
+	pcie = malloc(sizeof(*pcie));
+	if (!pcie)
+		return busno;
+	memset(pcie, 0, sizeof(*pcie));
+
+	hose = &pcie->hose;
+	hose->priv_data = pcie;
+	hose->first_busno = busno;
+	pcie->idx = num;
+	pcie->dbi = map_physmem(info->regs, PCIE_DBI_SIZE, MAP_NOCACHE);
+	pcie->va_cfg0 = map_physmem(info->cfg0_phys,
+				    info->cfg0_size,
+				    MAP_NOCACHE);
+	pcie->va_cfg1 = map_physmem(info->cfg1_phys,
+				    info->cfg1_size,
+				    MAP_NOCACHE);
+
+	/* outbound memory */
+	pci_set_region(&hose->regions[0],
+		       (pci_size_t)info->mem_bus,
+		       (phys_size_t)info->mem_phys,
+		       (pci_size_t)info->mem_size,
+		       PCI_REGION_MEM);
+
+	/* outbound io */
+	pci_set_region(&hose->regions[1],
+		       (pci_size_t)info->io_bus,
+		       (phys_size_t)info->io_phys,
+		       (pci_size_t)info->io_size,
+		       PCI_REGION_IO);
+
+	/* System memory space */
+	pci_set_region(&hose->regions[2],
+		       CONFIG_SYS_PCI_MEMORY_BUS,
+		       CONFIG_SYS_PCI_MEMORY_PHYS,
+		       CONFIG_SYS_PCI_MEMORY_SIZE,
+		       PCI_REGION_SYS_MEMORY);
+
+	hose->region_count = 3;
+
+	for (i = 0; i < hose->region_count; i++)
+		debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n",
+		      i,
+		      (u64)hose->regions[i].phys_start,
+		      (u64)hose->regions[i].bus_start,
+		      (u64)hose->regions[i].size,
+		      hose->regions[i].flags);
+
+	pci_set_ops(hose,
+		    pci_hose_read_config_byte_via_dword,
+		    pci_hose_read_config_word_via_dword,
+		    ls_pcie_read_config,
+		    pci_hose_write_config_byte_via_dword,
+		    pci_hose_write_config_word_via_dword,
+		    ls_pcie_write_config);
+
+	pci_hose_read_config_byte(hose, pdev, PCI_HEADER_TYPE, &header_type);
+	ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
+	printf("PCIe%u: %s ", info->pci_num,
+	       ep_mode ? "Endpoint" : "Root Complex");
+
+	linkup = ls_pcie_link_up(pcie);
+
+	if (!linkup) {
+		/* Let the user know there's no PCIe link */
+		printf("no link, regs @ 0x%lx\n", info->regs);
+		hose->last_busno = hose->first_busno;
+		return busno;
+	}
+
+	/* Print the negotiated PCIe link width */
+	pci_hose_read_config_word(hose, dev, PCIE_LINK_STA, &temp16);
+		printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
+		       (temp16 & 0xf), info->regs);
+
+	if (ep_mode)
+		return busno;
+
+	ls_pcie_setup_ctrl(pcie, info);
+
+	pci_register_hose(hose);
+
+	hose->last_busno = pci_hose_scan(hose);
+
+	printf("PCIe%x: Bus %02x - %02x\n",
+	       info->pci_num, hose->first_busno, hose->last_busno);
+
+	return hose->last_busno + 1;
+}
+
+int ls_pcie_init_board(int busno)
+{
+	struct ls_pcie_info info;
+
+#ifdef CONFIG_PCIE1
+	SET_LS_PCIE_INFO(info, 1);
+	busno = ls_pcie_init_ctrl(busno, PCIE1, &info);
+#endif
+
+#ifdef CONFIG_PCIE2
+	SET_LS_PCIE_INFO(info, 2);
+	busno = ls_pcie_init_ctrl(busno, PCIE2, &info);
+#endif
+
+#ifdef CONFIG_PCIE3
+	SET_LS_PCIE_INFO(info, 3);
+	busno = ls_pcie_init_ctrl(busno, PCIE3, &info);
+#endif
+
+#ifdef CONFIG_PCIE4
+	SET_LS_PCIE_INFO(info, 4);
+	busno = ls_pcie_init_ctrl(busno, PCIE4, &info);
+#endif
+
+	return busno;
+}
+
+void pci_init_board(void)
+{
+	ls_pcie_init_board(0);
+}
+
 #ifdef CONFIG_OF_BOARD_SETUP
 #include <libfdt.h>
 #include <fdt_support.h>
@@ -38,6 +495,14 @@ void ft_pcie_setup(void *blob, bd_t *bd)
 	#ifdef CONFIG_PCIE2
 	ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2);
 	#endif
+
+	#ifdef CONFIG_PCIE3
+	ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE3_ADDR, PCIE3);
+	#endif
+
+	#ifdef CONFIG_PCIE4
+	ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE4_ADDR, PCIE4);
+	#endif
 }
 
 #else
@@ -45,7 +510,3 @@ void ft_pcie_setup(void *blob, bd_t *bd)
 {
 }
 #endif
-
-void pci_init_board(void)
-{
-}