diff options
author | Tom Rini <trini@konsulko.com> | 2016-11-26 14:26:27 (GMT) |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2016-11-26 14:26:27 (GMT) |
commit | 8d0898544e0930974f39d9f13de2a874a501aa18 (patch) | |
tree | e79257510f56afa87294d9dad3638d6df9590113 /drivers | |
parent | ce4f2dbe1a066a42a995c6f48280e2e1a5df1c92 (diff) | |
parent | 6b388f0bed0e3d021128b4fc3c41da4572984e3b (diff) | |
download | u-boot-8d0898544e0930974f39d9f13de2a874a501aa18.tar.xz |
Merge git://git.denx.de/u-boot-rockchip
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/clk/rockchip/clk_rk3288.c | 7 | ||||
-rw-r--r-- | drivers/mtd/spi/spi_flash.c | 2 | ||||
-rw-r--r-- | drivers/power/regulator/regulator-uclass.c | 28 | ||||
-rw-r--r-- | drivers/spi/rk_spi.c | 44 | ||||
-rw-r--r-- | drivers/spi/spi-uclass.c | 18 | ||||
-rw-r--r-- | drivers/video/display-uclass.c | 18 | ||||
-rw-r--r-- | drivers/video/rockchip/rk_hdmi.c | 33 | ||||
-rw-r--r-- | drivers/video/rockchip/rk_vop.c | 16 | ||||
-rw-r--r-- | drivers/video/video-uclass.c | 3 |
9 files changed, 141 insertions, 28 deletions
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index ed97e87..d15504c 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -691,6 +691,13 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate) gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); switch (clk->id) { + case PLL_APLL: + /* We only support a fixed rate here */ + if (rate != 1800000000) + return -EINVAL; + rk3288_clk_configure_cpu(priv->cru, priv->grf); + new_rate = rate; + break; case CLK_DDR: new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate); break; diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 2576c2c..94c0b00 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -1138,7 +1138,7 @@ int spi_flash_scan(struct spi_flash *flash) return ret; #endif -#if CONFIG_IS_ENABLED(OF_CONTROL) +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) ret = spi_flash_decode_fdt(gd->fdt_blob, flash); if (ret) { debug("SF: FDT decode error\n"); diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 4434e36..52a1070 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -41,6 +41,27 @@ int regulator_get_value(struct udevice *dev) int regulator_set_value(struct udevice *dev, int uV) { const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); + struct dm_regulator_uclass_platdata *uc_pdata; + + uc_pdata = dev_get_uclass_platdata(dev); + if (uc_pdata->min_uV != -ENODATA && uV < uc_pdata->min_uV) + return -EINVAL; + if (uc_pdata->max_uV != -ENODATA && uV > uc_pdata->max_uV) + return -EINVAL; + + if (!ops || !ops->set_value) + return -ENOSYS; + + return ops->set_value(dev, uV); +} + +/* + * To be called with at most caution as there is no check + * before setting the actual voltage value. + */ +int regulator_set_value_force(struct udevice *dev, int uV) +{ + const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); if (!ops || !ops->set_value) return -ENOSYS; @@ -61,6 +82,13 @@ int regulator_get_current(struct udevice *dev) int regulator_set_current(struct udevice *dev, int uA) { const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); + struct dm_regulator_uclass_platdata *uc_pdata; + + uc_pdata = dev_get_uclass_platdata(dev); + if (uc_pdata->min_uA != -ENODATA && uA < uc_pdata->min_uA) + return -EINVAL; + if (uc_pdata->max_uA != -ENODATA && uA > uc_pdata->max_uA) + return -EINVAL; if (!ops || !ops->set_current) return -ENOSYS; diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c index 105ee4a..15cf0bd 100644 --- a/drivers/spi/rk_spi.c +++ b/drivers/spi/rk_spi.c @@ -12,6 +12,7 @@ #include <common.h> #include <clk.h> #include <dm.h> +#include <dt-structs.h> #include <errno.h> #include <spi.h> #include <linux/errno.h> @@ -27,6 +28,9 @@ DECLARE_GLOBAL_DATA_PTR; #define DEBUG_RK_SPI 0 struct rockchip_spi_platdata { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_rockchip_rk3288_spi of_plat; +#endif s32 frequency; /* Default clock frequency, -1 for none */ fdt_addr_t base; uint deactivate_delay_us; /* Delay to wait after deactivate */ @@ -106,6 +110,14 @@ static void spi_cs_activate(struct udevice *dev, uint cs) struct rockchip_spi_priv *priv = dev_get_priv(bus); struct rockchip_spi *regs = priv->regs; + /* If it's too soon to do another transaction, wait */ + if (plat->deactivate_delay_us && priv->last_transaction_us) { + ulong delay_us; /* The delay completed so far */ + delay_us = timer_get_us() - priv->last_transaction_us; + if (delay_us < plat->deactivate_delay_us) + udelay(plat->deactivate_delay_us - delay_us); + } + debug("activate cs%u\n", cs); writel(1 << cs, ®s->ser); if (plat->activate_delay_us) @@ -127,9 +139,29 @@ static void spi_cs_deactivate(struct udevice *dev, uint cs) priv->last_transaction_us = timer_get_us(); } +#if CONFIG_IS_ENABLED(OF_PLATDATA) +static int conv_of_platdata(struct udevice *dev) +{ + struct rockchip_spi_platdata *plat = dev->platdata; + struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat; + struct rockchip_spi_priv *priv = dev_get_priv(dev); + int ret; + + plat->base = dtplat->reg[0]; + plat->frequency = 20000000; + ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk); + if (ret < 0) + return ret; + dev->req_seq = 0; + + return 0; +} +#endif + static int rockchip_spi_ofdata_to_platdata(struct udevice *bus) { - struct rockchip_spi_platdata *plat = bus->platdata; +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rockchip_spi_platdata *plat = dev_get_platdata(bus); struct rockchip_spi_priv *priv = dev_get_priv(bus); const void *blob = gd->fdt_blob; int node = bus->of_offset; @@ -153,6 +185,7 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice *bus) debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n", __func__, (uint)plat->base, plat->frequency, plat->deactivate_delay_us); +#endif return 0; } @@ -164,6 +197,11 @@ static int rockchip_spi_probe(struct udevice *bus) int ret; debug("%s: probe\n", __func__); +#if CONFIG_IS_ENABLED(OF_PLATDATA) + ret = conv_of_platdata(bus); + if (ret) + return ret; +#endif priv->regs = (struct rockchip_spi *)plat->base; priv->last_transaction_us = timer_get_us(); @@ -369,7 +407,11 @@ static const struct udevice_id rockchip_spi_ids[] = { }; U_BOOT_DRIVER(rockchip_spi) = { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + .name = "rockchip_rk3288_spi", +#else .name = "rockchip_spi", +#endif .id = UCLASS_SPI, .of_match = rockchip_spi_ids, .ops = &rockchip_spi_ops, diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index d9c49e4..f59a701 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -108,6 +108,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, return dm_spi_xfer(slave->dev, bitlen, dout, din, flags); } +#if !CONFIG_IS_ENABLED(OF_PLATDATA) static int spi_child_post_bind(struct udevice *dev) { struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev); @@ -117,14 +118,16 @@ static int spi_child_post_bind(struct udevice *dev) return spi_slave_ofdata_to_platdata(gd->fdt_blob, dev->of_offset, plat); } +#endif static int spi_post_probe(struct udevice *bus) { +#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct dm_spi_bus *spi = dev_get_uclass_priv(bus); spi->max_hz = fdtdec_get_int(gd->fdt_blob, bus->of_offset, "spi-max-frequency", 0); - +#endif #if defined(CONFIG_NEEDS_MANUAL_RELOC) struct dm_spi_ops *ops = spi_get_ops(bus); @@ -274,7 +277,11 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, bool created = false; int ret; +#if CONFIG_IS_ENABLED(OF_PLATDATA) + ret = uclass_first_device_err(UCLASS_SPI, &bus); +#else ret = uclass_get_device_by_seq(UCLASS_SPI, busnum, &bus); +#endif if (ret) { printf("Invalid bus %d (err=%d)\n", busnum, ret); return ret; @@ -290,8 +297,11 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, debug("%s: Binding new device '%s', busnum=%d, cs=%d, driver=%s\n", __func__, dev_name, busnum, cs, drv_name); ret = device_bind_driver(bus, drv_name, dev_name, &dev); - if (ret) + if (ret) { + debug("%s: Unable to bind driver (ret=%d)\n", __func__, + ret); return ret; + } plat = dev_get_parent_platdata(dev); plat->cs = cs; plat->max_hz = speed; @@ -436,14 +446,18 @@ UCLASS_DRIVER(spi) = { .id = UCLASS_SPI, .name = "spi", .flags = DM_UC_FLAG_SEQ_ALIAS, +#if !CONFIG_IS_ENABLED(OF_PLATDATA) .post_bind = dm_scan_fdt_dev, +#endif .post_probe = spi_post_probe, .child_pre_probe = spi_child_pre_probe, .per_device_auto_alloc_size = sizeof(struct dm_spi_bus), .per_child_auto_alloc_size = sizeof(struct spi_slave), .per_child_platdata_auto_alloc_size = sizeof(struct dm_spi_slave_platdata), +#if !CONFIG_IS_ENABLED(OF_PLATDATA) .child_post_bind = spi_child_post_bind, +#endif }; UCLASS_DRIVER(spi_generic) = { diff --git a/drivers/video/display-uclass.c b/drivers/video/display-uclass.c index e4763de..e752eb0 100644 --- a/drivers/video/display-uclass.c +++ b/drivers/video/display-uclass.c @@ -23,10 +23,19 @@ int display_enable(struct udevice *dev, int panel_bpp, const struct display_timing *timing) { struct dm_display_ops *ops = display_get_ops(dev); + struct display_plat *disp_uc_plat; + int ret; if (!ops || !ops->enable) return -ENOSYS; - return ops->enable(dev, panel_bpp, timing); + ret = ops->enable(dev, panel_bpp, timing); + if (ret) + return ret; + + disp_uc_plat = dev_get_uclass_platdata(dev); + disp_uc_plat->in_use = true; + + return 0; } int display_read_timing(struct udevice *dev, struct display_timing *timing) @@ -48,6 +57,13 @@ int display_read_timing(struct udevice *dev, struct display_timing *timing) return edid_get_timing(buf, ret, timing, &panel_bits_per_colour); } +bool display_in_use(struct udevice *dev) +{ + struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev); + + return disp_uc_plat->in_use; +} + UCLASS_DRIVER(display) = { .id = UCLASS_DISPLAY, .name = "display", diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c index 7976c5e..032b1de 100644 --- a/drivers/video/rockchip/rk_hdmi.c +++ b/drivers/video/rockchip/rk_hdmi.c @@ -132,8 +132,8 @@ static const u32 csc_coeff_default[3][4] = { static void hdmi_set_clock_regenerator(struct rk3288_hdmi *regs, u32 n, u32 cts) { - u8 cts3; - u8 n3; + uint cts3; + uint n3; /* first set ncts_atomic_write (if present) */ n3 = HDMI_AUD_N3_NCTS_ATOMIC_WRITE; @@ -199,7 +199,7 @@ static void hdmi_audio_set_samplerate(struct rk3288_hdmi *regs, u32 pixel_clk) static void hdmi_video_sample(struct rk3288_hdmi *regs) { u32 color_format = 0x01; - u8 val; + uint val; val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & @@ -256,7 +256,7 @@ static void hdmi_video_packetize(struct rk3288_hdmi *regs) u32 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; u32 remap_size = HDMI_VP_REMAP_YCC422_16BIT; u32 color_depth = 0; - u8 val, vp_conf; + uint val, vp_conf; /* set the packetizer registers */ val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & @@ -297,7 +297,7 @@ static void hdmi_video_packetize(struct rk3288_hdmi *regs) output_select); } -static inline void hdmi_phy_test_clear(struct rk3288_hdmi *regs, u8 bit) +static inline void hdmi_phy_test_clear(struct rk3288_hdmi *regs, uint bit) { clrsetbits_le32(®s->phy_tst0, HDMI_PHY_TST0_TSTCLR_MASK, bit << HDMI_PHY_TST0_TSTCLR_OFFSET); @@ -382,7 +382,7 @@ static void hdmi_phy_sel_interface_control(struct rk3288_hdmi *regs, static int hdmi_phy_configure(struct rk3288_hdmi *regs, u32 mpixelclock) { ulong start; - u8 i, val; + uint i, val; writel(HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, ®s->mc_flowctrl); @@ -481,8 +481,8 @@ static int hdmi_phy_init(struct rk3288_hdmi *regs, uint mpixelclock) static void hdmi_av_composer(struct rk3288_hdmi *regs, const struct display_timing *edid) { - u8 mdataenablepolarity = 1; - u8 inv_val; + bool mdataenablepolarity = true; + uint inv_val; uint hbl; uint vbl; @@ -553,7 +553,7 @@ static void hdmi_av_composer(struct rk3288_hdmi *regs, /* hdmi initialization step b.4 */ static void hdmi_enable_video_path(struct rk3288_hdmi *regs) { - u8 clkdis; + uint clkdis; /* control period minimum duration */ writel(12, ®s->fc_ctrldur); @@ -580,7 +580,7 @@ static void hdmi_enable_video_path(struct rk3288_hdmi *regs) /* workaround to clear the overflow condition */ static void hdmi_clear_overflow(struct rk3288_hdmi *regs) { - u8 val, count; + uint val, count; /* tmds software reset */ writel((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, ®s->mc_swrstz); @@ -614,7 +614,7 @@ static void hdmi_audio_fifo_reset(struct rk3288_hdmi *regs) static void hdmi_init_interrupt(struct rk3288_hdmi *regs) { - u8 ih_mute; + uint ih_mute; /* * boot up defaults are: @@ -650,11 +650,11 @@ static void hdmi_init_interrupt(struct rk3288_hdmi *regs) writel(HDMI_IH_PHY_STAT0_HPD, ®s->ih_phy_stat0); } -static u8 hdmi_get_plug_in_status(struct rk3288_hdmi *regs) +static int hdmi_get_plug_in_status(struct rk3288_hdmi *regs) { - u8 val = readl(®s->phy_stat0) & HDMI_PHY_HPD; + uint val = readl(®s->phy_stat0) & HDMI_PHY_HPD; - return !!(val); + return !!val; } static int hdmi_wait_for_hpd(struct rk3288_hdmi *regs) @@ -753,7 +753,7 @@ static int hdmi_read_edid(struct rk3288_hdmi *regs, int block, u8 *buff) return edid_read_err; } -static u8 pre_buf[] = { +static const u8 pre_buf[] = { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x04, 0x69, 0xfa, 0x23, 0xc8, 0x28, 0x01, 0x00, 0x10, 0x17, 0x01, 0x03, 0x80, 0x33, 0x1d, 0x78, @@ -899,7 +899,8 @@ static int rk_hdmi_probe(struct udevice *dev) rk_setreg(&priv->grf->soc_con6, 1 << 15); /* hdmi data from vop id */ - rk_setreg(&priv->grf->soc_con6, (vop_id == 1) ? (1 << 4) : (1 << 4)); + rk_clrsetreg(&priv->grf->soc_con6, 1 << 4, + (vop_id == 1) ? (1 << 4) : 0); ret = hdmi_wait_for_hpd(priv->regs); if (ret < 0) { diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c index c6d88d9..eab5486 100644 --- a/drivers/video/rockchip/rk_vop.c +++ b/drivers/video/rockchip/rk_vop.c @@ -195,7 +195,6 @@ int rk_display_init(struct udevice *dev, ulong fbbase, struct udevice *disp; int ret, remote, i, offset; struct display_plat *disp_uc_plat; - struct udevice *dev_clk; struct clk clk; vop_id = fdtdec_get_int(blob, ep_node, "reg", -1); @@ -222,6 +221,11 @@ int rk_display_init(struct udevice *dev, ulong fbbase, disp_uc_plat = dev_get_uclass_platdata(disp); debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat); + if (display_in_use(disp)) { + debug(" - device in use\n"); + return -EBUSY; + } + disp_uc_plat->source_id = remote_vop_id; disp_uc_plat->src_dev = dev; @@ -238,11 +242,7 @@ int rk_display_init(struct udevice *dev, ulong fbbase, return ret; } - ret = rockchip_get_clk(&dev_clk); - if (!ret) { - clk.id = DCLK_VOP0 + remote_vop_id; - ret = clk_request(dev_clk, &clk); - } + ret = clk_get_by_index(dev, 1, &clk); if (!ret) ret = clk_set_rate(&clk, timing.pixelclock.typ); if (ret) { @@ -316,6 +316,10 @@ static int rk_vop_probe(struct udevice *dev) /* * Try all the ports until we find one that works. In practice this * tries EDP first if available, then HDMI. + * + * Note that rockchip_vop_set_clk() always uses NPLL as the source + * clock so it is currently not possible to use more than one display + * device simultaneously. */ port = fdt_subnode_offset(blob, dev->of_offset, "port"); if (port < 0) diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index 11ca793..3036e3a 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -117,7 +117,8 @@ void video_sync(struct udevice *vid) if (priv->flush_dcache) { flush_dcache_range((ulong)priv->fb, - (ulong)priv->fb + priv->fb_size); + ALIGN((ulong)priv->fb + priv->fb_size, + CONFIG_SYS_CACHELINE_SIZE)); } #elif defined(CONFIG_VIDEO_SANDBOX_SDL) struct video_priv *priv = dev_get_uclass_priv(vid); |