diff options
author | Simon Glass <sjg@chromium.org> | 2016-01-30 23:38:01 (GMT) |
---|---|---|
committer | Tom Warren <twarren@nvidia.com> | 2016-02-16 16:17:53 (GMT) |
commit | 91c08afe66f8b24798389cf628210844b1dfa215 (patch) | |
tree | e7f47497a17896b2b5ae2de51c61c63005159bca /drivers | |
parent | 41fa035ce1480aa87d42e4af0ed8ea841944c2c9 (diff) | |
download | u-boot-91c08afe66f8b24798389cf628210844b1dfa215.tar.xz |
tegra: video: Move LCD driver to use the DM PWM driver
Use the driver-model PWM driver in preference to the old code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/pwm/Kconfig | 1 | ||||
-rw-r--r-- | drivers/video/tegra.c | 20 |
2 files changed, 17 insertions, 4 deletions
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index e5880ac..6f0d61e 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -20,6 +20,7 @@ config PWM_ROCKCHIP config PWM_TEGRA bool "Enable support for the Tegra PWM" + depends on DM_PWM help This PWM is found on Tegra 20 and other Nvidia SoCs. It supports four channels with a programmable period and duty cycle. Only a diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c index ccd9c08..7fd10e6 100644 --- a/drivers/video/tegra.c +++ b/drivers/video/tegra.c @@ -6,6 +6,7 @@ #include <common.h> #include <dm.h> #include <fdtdec.h> +#include <pwm.h> #include <video.h> #include <asm/system.h> #include <asm/gpio.h> @@ -68,6 +69,7 @@ struct tegra_lcd_priv { unsigned pixel_clock; /* Pixel clock in Hz */ uint horiz_timing[FDT_LCD_TIMING_COUNT]; /* Horizontal timing */ uint vert_timing[FDT_LCD_TIMING_COUNT]; /* Vertical timing */ + struct udevice *pwm; int pwm_channel; /* PWM channel to use for backlight */ enum lcd_cache_t cache_type; @@ -400,7 +402,8 @@ static int handle_stage(const void *blob, struct tegra_lcd_priv *priv) pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM); pinmux_tristate_disable(PMUX_PINGRP_GPU); - pwm_enable(priv->pwm_channel, 32768, 0xdf, 1); + pwm_set_config(priv->pwm, priv->pwm_channel, 0xdf, 0xff); + pwm_set_enable(priv->pwm, priv->pwm_channel, true); break; case STAGE_BACKLIGHT_EN: if (dm_gpio_is_valid(&priv->backlight_en)) @@ -504,12 +507,14 @@ static int tegra_lcd_probe(struct udevice *dev) static int tegra_lcd_ofdata_to_platdata(struct udevice *dev) { struct tegra_lcd_priv *priv = dev_get_priv(dev); + struct fdtdec_phandle_args args; const void *blob = gd->fdt_blob; int node = dev->of_offset; int front, back, ref; int panel_node; int rgb; int bpp, bit; + int ret; priv->disp = (struct disp_ctlr *)dev_get_addr(dev); if (!priv->disp) { @@ -575,12 +580,19 @@ static int tegra_lcd_ofdata_to_platdata(struct udevice *dev) return -EINVAL; } - priv->pwm_channel = pwm_request(blob, panel_node, "nvidia,pwm"); - if (priv->pwm_channel < 0) { - debug("%s: Unable to request PWM channel\n", __func__); + if (fdtdec_parse_phandle_with_args(blob, panel_node, "nvidia,pwm", + "#pwm-cells", 0, 0, &args)) { + debug("%s: Unable to decode PWM\n", __func__); return -EINVAL; } + ret = uclass_get_device_by_of_offset(UCLASS_PWM, args.node, &priv->pwm); + if (ret) { + debug("%s: Unable to find PWM\n", __func__); + return -EINVAL; + } + priv->pwm_channel = args.args[0]; + priv->cache_type = fdtdec_get_int(blob, panel_node, "nvidia,cache-type", FDT_LCD_CACHE_WRITE_BACK_FLUSH); |