diff options
author | Simon Glass <sjg@chromium.org> | 2012-07-29 20:53:25 (GMT) |
---|---|---|
committer | Tom Warren <twarren@nvidia.com> | 2012-09-07 20:54:30 (GMT) |
commit | b572595ee95829ab62e354c55a8fbd0f4db23935 (patch) | |
tree | 18ce59921123f5b98f47e4845bef96f191593cd4 /drivers | |
parent | 057df193b40d31799d41d43bc832a972f658bfe4 (diff) | |
download | u-boot-b572595ee95829ab62e354c55a8fbd0f4db23935.tar.xz |
nand: Try to align the default buffers
The NAND layer needs to use cache-aligned buffers by default. Towards this
goal. align the default buffers and their members according to the minimum
DMA alignment defined for the architecture.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/mtd/nand/nand_base.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index bfd668f..891af1f 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2936,7 +2936,8 @@ int nand_scan_tail(struct mtd_info *mtd) struct nand_chip *chip = mtd->priv; if (!(chip->options & NAND_OWN_BUFFERS)) - chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL); + chip->buffers = memalign(ARCH_DMA_MINALIGN, + sizeof(*chip->buffers)); if (!chip->buffers) return -ENOMEM; |