diff options
| author | Jon Loeliger <jdl@freescale.com> | 2005-07-25 19:05:07 (GMT) |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2005-07-25 19:05:07 (GMT) |
| commit | d9b94f28a442b0013caef99de084d7b72e2d4607 (patch) | |
| tree | 1b293a551e021a4a696717231ec03206d9f172de /include/asm-ppc/processor.h | |
| parent | 288693abe1f7c23e69479fd85c2c0d8d7fdbf8f2 (diff) | |
| download | u-boot-d9b94f28a442b0013caef99de084d7b72e2d4607.tar.xz | |
* Patch by Jon Loeliger, 2005-05-05
Implemented support for MPC8548CDS board.
Added DDR II support based on SPD values for MPC85xx boards.
This roll-up patch also includes bugfies for the previously
published patches:
DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
Diffstat (limited to 'include/asm-ppc/processor.h')
| -rw-r--r-- | include/asm-ppc/processor.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 71fadbc..20949dc 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -420,6 +420,7 @@ #define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ #define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ #define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ +#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */ #define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ #define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ @@ -584,6 +585,7 @@ #define MAS4 SPRN_MAS4 #define MAS5 SPRN_MAS5 #define MAS6 SPRN_MAS6 +#define MAS7 SPRN_MAS7 /* Device Control Registers */ @@ -792,6 +794,8 @@ #define SVR_8560 0x8070 #define SVR_8555 0x8079 #define SVR_8541 0x807A +#define SVR_8548 0x8031 +#define SVR_8548_E 0x8039 /* I am just adding a single entry for 8260 boards. I think we may be |