diff options
| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2013-09-10 12:03:12 (GMT) |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-10-16 23:13:12 (GMT) |
| commit | 4544fd2976ba353689182c28a4d0673ded22e831 (patch) | |
| tree | 9c01150497cd25930173ad2a7344fba418d69e28 /include/configs/BSC9131RDB.h | |
| parent | 62c6ef336d8d315e3aed1fc7d4235db210e1c75d (diff) | |
| download | u-boot-4544fd2976ba353689182c28a4d0673ded22e831.tar.xz | |
board/bsc9131rdb: Update IFC timings for NAND flash
Current IFC timings for NAND flash are not able to support existing
K9F1G08U0B and new K9F1G08U0D flash.
so Update the timings to support both.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Diffstat (limited to 'include/configs/BSC9131RDB.h')
| -rw-r--r-- | include/configs/BSC9131RDB.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 948394e..1d06c50 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -181,18 +181,18 @@ extern unsigned long get_sdram_size(void); | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ /* NAND Flash Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x08) \ - | FTIM0_NAND_TWP(0x06) \ - | FTIM0_NAND_TWCHT(0x03) \ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ + | FTIM0_NAND_TWP(0x05) \ + | FTIM0_NAND_TWCHT(0x02) \ | FTIM0_NAND_TWH(0x04)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x18) \ - | FTIM1_NAND_TWBE(0x23) \ - | FTIM1_NAND_TRR(0x08) \ +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \ + | FTIM1_NAND_TWBE(0x1E) \ + | FTIM1_NAND_TRR(0x07) \ | FTIM1_NAND_TRP(0x05)) #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ | FTIM2_NAND_TREH(0x04) \ - | FTIM2_NAND_TWHRE(0x3f)) -#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x22) + | FTIM2_NAND_TWHRE(0x11)) +#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 |