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author | Becky Bruce <beckyb@kernel.crashing.org> | 2010-12-17 23:17:56 (GMT) |
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committer | Kumar Gala <galak@kernel.crashing.org> | 2011-01-14 07:32:19 (GMT) |
commit | 38dba0c2ff685e3f8276a236bd70eaa09c84ead5 (patch) | |
tree | fc3365f6bdd25dfe23f2ec8c02926907613c8520 /include/configs/TQM85xx.h | |
parent | 6b1ef2a6a553c33e74c5e50c77b55d40af669be3 (diff) | |
download | u-boot-38dba0c2ff685e3f8276a236bd70eaa09c84ead5.tar.xz |
mpc85xx boards: initdram() cleanup/bugfix
Correct initdram to use phys_size_t to represent the size of
dram; instead of changing this all over the place, and correcting
all the other random errors I've noticed, create a
common initdram that is used by all non-corenet 85xx parts. Most
of the initdram() functions were identical, with 2 common differences:
1) DDR tlbs for the fixed_sdram case were set up in initdram() on
some boards, and were part of the tlb_table on others. I have
changed them all over to the initdram() method - we shouldn't
be accessing dram before this point so they don't need to be
done sooner, and this seems cleaner.
2) Parts that require the DDR11 erratum workaround had different
implementations - I have adopted the version from the Freescale
errata document. It also looks like some of the versions were
buggy, and, depending on timing, could have resulted in the
DDR controller being disabled. This seems bad.
The xpedite boards had a common/fsl_8xxx_ddr.c; with this
change only the 517 board uses this so I have moved the ddr code
into that board's directory in xpedite517x.c
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/configs/TQM85xx.h')
-rw-r--r-- | include/configs/TQM85xx.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 890d6d9..febe95d 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -147,6 +147,10 @@ * DDR Setup */ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#if defined(CONFIG_TQM_BIGFLASH) || \ + (!defined(CONFIG_TQM8548_AG) && !defined(CONFIG_TQM8548_BE)) +#define CONFIG_SYS_PPC_DDR_WIMGE (MAS2_I | MAS2_G) +#endif #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #ifdef CONFIG_TQM8548_AG #define CONFIG_VERY_BIG_RAM |