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| author | Priyanka Jain <Priyanka.Jain@freescale.com> | 2013-04-04 04:01:54 (GMT) |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2013-06-20 21:09:08 (GMT) |
| commit | 765b0bdb899d614d0455f19548901b79f2baa66c (patch) | |
| tree | 7508adf27d2e7f7ae32c925ba555f33528a1b1e8 /include/configs/ebony.h | |
| parent | 087cf44fcd237d965ecccd6cf9e52de8d3c51a2e (diff) | |
| download | u-boot-765b0bdb899d614d0455f19548901b79f2baa66c.tar.xz | |
board/bsc9131rdb: Add DSP side tlb and laws
BSC9131RDB is a Freescale Reference Design Board for
BSC9131 SoC which is a integrated device that contains
one powerpc e500v2 core and one DSP starcore.
To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 memory
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'include/configs/ebony.h')
0 files changed, 0 insertions, 0 deletions