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author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-07-01 18:52:51 (GMT) |
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committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-07-01 18:52:51 (GMT) |
commit | 304f936aeaab0c3cc9d5af438fd3498ac7682991 (patch) | |
tree | 6b50ccc855dff4717749974630d258ba786811d0 /include/configs/exynos5420.h | |
parent | 019b57cc1d280c3768e2e8a7ff22e07a64c2f670 (diff) | |
parent | 5287d595449512385e25f5afcb68a130bf08bae6 (diff) | |
download | u-boot-304f936aeaab0c3cc9d5af438fd3498ac7682991.tar.xz |
Merge remote-tracking branch 'u-boot-samsung/master'
Conflicts:
boards.cfg
Conflict was trivial between goni maintainer change and
lager_nor removal.
Diffstat (limited to 'include/configs/exynos5420.h')
-rw-r--r-- | include/configs/exynos5420.h | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/include/configs/exynos5420.h b/include/configs/exynos5420.h new file mode 100644 index 0000000..d2a9556 --- /dev/null +++ b/include/configs/exynos5420.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * + * Configuration settings for the SAMSUNG EXYNOS5420 SoC + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_EXYNOS5420_H +#define __CONFIG_EXYNOS5420_H + +#define CONFIG_EXYNOS5420 /* which is in a Exynos5 Family */ + +#define MACH_TYPE_SMDK5420 8002 +#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5420 + +#define CONFIG_VAR_SIZE_SPL + +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_TEXT_BASE 0x23E00000 +#ifdef CONFIG_VAR_SIZE_SPL +#define CONFIG_SPL_TEXT_BASE 0x02024410 +#else +#define CONFIG_SPL_TEXT_BASE 0x02024400 +#endif +#define CONFIG_IRAM_TOP 0x02074000 + +#define CONFIG_SPL_MAX_FOOTPRINT (30 * 1024) + +#define CONFIG_DEVICE_TREE_LIST "exynos5420-peach-pit exynos5420-smdk5420" + +#define CONFIG_MAX_I2C_NUM 11 + +/* Enable FIT support and comparison */ +#define CONFIG_FIT +#define CONFIG_FIT_BEST_MATCH + +#define CONFIG_BOARD_REV_GPIO_COUNT 2 + +#define CONFIG_BOOTCOMMAND "mmc read 20007000 451 2000; bootm 20007000" + +/* + * Put the initial stack pointer 1KB below this to allow room for the + * SPL marker. This value is arbitrary, but gd_t is placed starting here. + */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) + +/* DRAM Memory Banks */ +#define CONFIG_NR_DRAM_BANKS 7 +#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ + +#endif /* __CONFIG_EXYNOS5420_H */ |