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| author | Tom Rini <trini@konsulko.com> | 2017-05-26 15:19:27 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-05-26 15:19:27 (GMT) |
| commit | 380e86f361e4e2aef83295972863654fde157560 (patch) | |
| tree | 5b1f04c1c763f6c06ae099a6eadac4eb2eb6d6b8 /include/configs/ls1046a_common.h | |
| parent | 8dc1b17f14c9201c7d0da0f33e404a7e051b2ec6 (diff) | |
| parent | 7676074ac756ab9566d52544cc836f7b93f80b37 (diff) | |
| download | u-boot-380e86f361e4e2aef83295972863654fde157560.tar.xz | |
Merge git://git.denx.de/u-boot-fsl-qoriq
Diffstat (limited to 'include/configs/ls1046a_common.h')
| -rw-r--r-- | include/configs/ls1046a_common.h | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 1fbafaa..b66b8ac 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -138,6 +138,16 @@ #define CONFIG_SYS_I2C_MXC_I2C3 #define CONFIG_SYS_I2C_MXC_I2C4 +/* PCIe */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define CONFIG_PCIE3 /* PCIE controller 3 */ + +#ifdef CONFIG_PCI +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_CMD_PCI +#endif + /* Command line configuration */ /* MMC */ @@ -163,23 +173,23 @@ /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is * about 1MB (2048 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800). */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800) #elif defined(CONFIG_QSPI_BOOT) #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_FMAN_FW_ADDR 0x40300000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000 #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_CS 0 #define CONFIG_ENV_SPI_MAX_HZ 1000000 #define CONFIG_ENV_SPI_MODE 0x03 #elif defined(CONFIG_NAND_BOOT) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_FMAN_FW_ADDR 0x60300000 +#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) |