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| author | Stefan Roese <sr@denx.de> | 2015-12-10 14:02:38 (GMT) |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2016-01-14 13:08:59 (GMT) |
| commit | 698ffab239609e75b8de8f7009c06311e8b0b21a (patch) | |
| tree | e0f126720e8bcae796da79efdc45c2014a6989ed /include/configs/maxbcm.h | |
| parent | bf0db8b82a0f2e1abcb073fe0b72e6b4ba7c5fe0 (diff) | |
| download | u-boot-698ffab239609e75b8de8f7009c06311e8b0b21a.tar.xz | |
arm: mvebu: Make ECC support configurable on Armada XP
Currently, ECC support is enabled for all Armada XP boards. So the
DDR3 driver tries to configure the controller with ECC support, even
on boards without ECC. This patch makes this ECC optional which now
can be configured on a board-per-board basis.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Phil Sutter <phil@nwl.cc>
Diffstat (limited to 'include/configs/maxbcm.h')
| -rw-r--r-- | include/configs/maxbcm.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index 49e83c0..23e5526 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -108,5 +108,6 @@ /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ #define CONFIG_SYS_MVEBU_DDR_AXP #define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ +#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ #endif /* _CONFIG_DB_MV7846MP_GP_H */ |