diff options
| author | Fabien Parent <fparent@baylibre.com> | 2016-11-29 13:23:39 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-12-03 18:21:14 (GMT) |
| commit | a5ab44f69bc4809cfaeea2fdb4e391dc828f49a1 (patch) | |
| tree | e5b0aaf689e676cc427d5a356649866ff550713a /include/configs/omapl138_lcdk.h | |
| parent | cd895dcbe0e2ee538c5fd9664f3ca4a17f57d83c (diff) | |
| download | u-boot-a5ab44f69bc4809cfaeea2fdb4e391dc828f49a1.tar.xz | |
davinci: omapl138_lcdk: configure ddr2
The SPL is unable to load u-boot because the DDR2 is not configured.
Configure the DDR2.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'include/configs/omapl138_lcdk.h')
| -rw-r--r-- | include/configs/omapl138_lcdk.h | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 854fc47..9db9cea 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -79,6 +79,47 @@ #define CONFIG_SYS_DA850_PLL1_PLLM 21 /* + * DDR2 memory configuration + */ +#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ + DV_DDR_PHY_EXT_STRBEN | \ + (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDBCR ( \ + (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ + (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ + (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ + (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ + (4 << DV_DDR_SDCR_CL_SHIFT) | \ + (3 << DV_DDR_SDCR_IBANK_SHIFT) | \ + (2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) + +/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ +#define CONFIG_SYS_DA850_DDR2_SDBCR2 0 + +#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ + (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \ + (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ + (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ + (2 << DV_DDR_SDTMR1_WR_SHIFT) | \ + (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \ + (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ + (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ + (1 << DV_DDR_SDTMR1_WTR_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ + (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ + (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ + (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ + (10 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ + (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ + (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ + (2 << DV_DDR_SDTMR2_CKE_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492 +#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 + +/* * Serial Driver info */ #define CONFIG_SYS_NS16550_SERIAL |