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authorStephen Warren <swarren@nvidia.com>2016-07-13 19:45:31 (GMT)
committerSimon Glass <sjg@chromium.org>2016-07-27 22:29:56 (GMT)
commit61f5ddcb7a997f7b7bca3680cd6f67e60e616841 (patch)
treeca5dcfb1d2335fa819cc7e36ea6295a6d12a4898 /include/dm
parent1e2b3ef8653417f296ee23f32c28abfc086529dd (diff)
downloadu-boot-61f5ddcb7a997f7b7bca3680cd6f67e60e616841.tar.xz
Add a power domain framework/uclass
Many SoCs allow power to be applied to or removed from portions of the SoC (power domains). This may be used to save power. This API provides the means to control such power management hardware. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include/dm')
-rw-r--r--include/dm/uclass-id.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index c5cdfc7..eb78c4d 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -59,6 +59,7 @@ enum uclass_id {
UCLASS_PINCTRL, /* Pinctrl (pin muxing/configuration) device */
UCLASS_PMIC, /* PMIC I/O device */
UCLASS_PWM, /* Pulse-width modulator */
+ UCLASS_POWER_DOMAIN, /* (SoC) Power domains */
UCLASS_PWRSEQ, /* Power sequence device */
UCLASS_RAM, /* RAM controller */
UCLASS_REGULATOR, /* Regulator device */