aspeed: Add basic ast2500-specific drivers and configuration

Clock Driver

This driver is ast2500-specific and is not compatible with earlier
versions of this chip. The differences are not that big, but they are
in somewhat random places, so making it compatible with ast2400 is not
worth the effort at the moment.

SDRAM MC driver

The driver is very ast2500-specific and is completely incompatible
with previous versions of the chip.

The memory controller is very poorly documented by Aspeed in the
datasheet, with any mention of the whole range of registers missing. The
initialization procedure has been basically taken from Aspeed SDK, where
it is implemented in assembly. Here it is rewritten in C, with very limited
understanding of what exactly it is doing.
Reviewed-by: Simon Glass <sjg@chromium.org>

1 files changed, 29 insertions, 0 deletions

diff --git a/include/dt-bindings/clock/ast2500-scu.h b/include/dt-bindings/clock/ast2500-scu.h
new file mode 100644
index 0000000..ca58b12
--- /dev/null
+++ b/include/dt-bindings/clock/ast2500-scu.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2016 Google Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Core Clocks */
+#define PLL_HPLL	1
+#define PLL_DPLL	2
+#define PLL_D2PLL	3
+#define PLL_MPLL	4
+#define ARMCLK		5
+
+
+/* Bus Clocks, derived from core clocks */
+#define BCLK_PCLK	101
+#define BCLK_LHCLK	102
+#define BCLK_MACCLK	103
+#define BCLK_SDCLK	104
+#define BCLK_ARMCLK	105
+
+#define MCLK_DDR	201
+
+/* Special clocks */
+#define PCLK_UART1	501
+#define PCLK_UART2	502
+#define PCLK_UART3	503
+#define PCLK_UART4	504
+#define PCLK_UART5	505