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| author | York Sun <yorksun@freescale.com> | 2014-09-05 05:52:41 (GMT) |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-09-08 17:30:34 (GMT) |
| commit | d28cb6714216cc9e6bfdc1fa333d5dcd174207bd (patch) | |
| tree | ce6fe8fcaf3297e38b8330d8d5bdbb345c2f63f6 /include/fsl_ddr_sdram.h | |
| parent | 19060bd886381a58cfe335c2f13b6111ed936dd5 (diff) | |
| download | u-boot-d28cb6714216cc9e6bfdc1fa333d5dcd174207bd.tar.xz | |
driver/ddr/freescale: Add support of accumulate ECC
If less than 8 ECC pins are used for DDR data bus width smaller than 64
bits, the 8-bit ECC code will be transmitted/received across several beats,
and it will be used to check 64-bits of data once 8-bits of ECC are
accumulated.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include/fsl_ddr_sdram.h')
0 files changed, 0 insertions, 0 deletions