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| author | Dipen Dudhat <dipen.dudhat@freescale.com> | 2009-10-05 10:11:58 (GMT) |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2010-04-24 02:02:30 (GMT) |
| commit | 77c1458d130d33704472db9c88d2310c8fc90f4c (patch) | |
| tree | e08d7beab6ad02b2e16f719a9869c98afe05c41d /include/fsl_esdhc.h | |
| parent | a47a12becf66f02a56da91c161e2edb625e9f20c (diff) | |
| download | u-boot-77c1458d130d33704472db9c88d2310c8fc90f4c.tar.xz | |
ppc/85xx: PIO Support for FSL eSDHC Controller Driver
On some Freescale SoC Internal DMA of eSDHC controller has bug.
So PIO Mode has been introduced to do data transfer using CPU.
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Diffstat (limited to 'include/fsl_esdhc.h')
| -rw-r--r-- | include/fsl_esdhc.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index f9ae15a..477bbd7 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -90,6 +90,7 @@ #define PRSSTAT_CDPL (0x00040000) #define PRSSTAT_CINS (0x00010000) #define PRSSTAT_BREN (0x00000800) +#define PRSSTAT_BWEN (0x00000400) #define PRSSTAT_DLA (0x00000004) #define PRSSTAT_CICHB (0x00000002) #define PRSSTAT_CIDHB (0x00000001) @@ -121,6 +122,7 @@ #define XFERTYP_DMAEN 0x00000001 #define CINS_TIMEOUT 1000 +#define PIO_TIMEOUT 100000 #define DSADDR 0x2e004 |