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authorPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>2016-07-19 10:24:22 (GMT)
committerYork Sun <york.sun@nxp.com>2016-08-02 16:45:56 (GMT)
commit9c3fca2a79be3d9d67d7766bbd85efc941bcb237 (patch)
tree8e2be972cad67b3fe5f7ec4fa47ac992c99729bd /include/fsl_mmdc.h
parent3b4dbd37dcd0b851f39dda1ff212d6ef902d4db7 (diff)
downloadu-boot-9c3fca2a79be3d9d67d7766bbd85efc941bcb237.tar.xz
armv8: ls1012a: Enable DDR row-bank-column decoding
Enable DDR row-bank-column decoding to decode DDR address as row-bank-column instead of bank-row-column for improving performance of serial data transfers. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'include/fsl_mmdc.h')
-rw-r--r--include/fsl_mmdc.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h
index 281a819..833696b 100644
--- a/include/fsl_mmdc.h
+++ b/include/fsl_mmdc.h
@@ -12,7 +12,7 @@
#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_1 0xff328f64
#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_2 0x01ff00db
-#define CONFIG_SYS_MMDC_CORE_MISC 0x00000680
+#define CONFIG_SYS_MMDC_CORE_MISC 0x00001680
#define CONFIG_SYS_MMDC_PHY_MEASURE_UNIT 0x00000800
#define CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY 0x00002000
#define CONFIG_SYS_MMDC_PHY_ODT_CTRL 0x0000022a