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| author | Ruchika Gupta <ruchika.gupta@freescale.com> | 2014-09-09 06:20:31 (GMT) |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-10-16 21:16:50 (GMT) |
| commit | 028dbb8db1d18c5835ab34659f9ef7a516571524 (patch) | |
| tree | b6c94157e8a8483a025b2ec4591df115422fe3ae /include/fsl_sec.h | |
| parent | 48ef0d2a1002d3da0bf7ed13d0959bcbf782c792 (diff) | |
| download | u-boot-028dbb8db1d18c5835ab34659f9ef7a516571524.tar.xz | |
fsl_sec : Change accessor function to take care of endianness
SEC registers can be of type Little Endian or big Endian depending upon
Freescale SoC. Here SoC defines the register type of SEC IP.
So update acessor functions with common SEC acessor functions to take care
both type of endianness.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include/fsl_sec.h')
| -rw-r--r-- | include/fsl_sec.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/include/fsl_sec.h b/include/fsl_sec.h index b31999f..a11f58d 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -11,6 +11,22 @@ #include <common.h> #include <asm/io.h> +#ifdef CONFIG_SYS_FSL_SEC_LE +#define sec_in32(a) in_le32(a) +#define sec_out32(a, v) out_le32(a, v) +#define sec_in16(a) in_le16(a) +#define sec_clrbits32 clrbits_le32 +#define sec_setbits32 setbits_le32 +#elif defined(CONFIG_SYS_FSL_SEC_BE) +#define sec_in32(a) in_be32(a) +#define sec_out32(a, v) out_be32(a, v) +#define sec_in16(a) in_be16(a) +#define sec_clrbits32 clrbits_be32 +#define sec_setbits32 setbits_be32 +#else +#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined +#endif + /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */ #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 typedef struct ccsr_sec { |