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| author | Russ Dill <Russ.Dill@ti.com> | 2016-07-21 11:28:31 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-07-25 16:00:06 (GMT) |
| commit | 3325b06556b78a2afdaaa781765b505f7d1f8ae4 (patch) | |
| tree | e4627e24ab3481ade5da8a719434f871ce1319e7 /include/i2s.h | |
| parent | 492716662fbdc08e254dda2c209b320e2bf6c837 (diff) | |
| download | u-boot-3325b06556b78a2afdaaa781765b505f7d1f8ae4.tar.xz | |
ARM: am33xx: Fix DDR init delay placement
The delay needs to be before the write to ref_ctrl register
which initiates refreshes. An improper initialization sequence
generates an L3 noc error.
Signed-off-by: Russ Dill <Russ.Dill@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'include/i2s.h')
0 files changed, 0 insertions, 0 deletions