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| author | Dave Liu <daveliu@freescale.com> | 2009-03-27 06:32:43 (GMT) |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2009-06-09 20:58:05 (GMT) |
| commit | 1b5291dddf5f16c7ae10e3cb165882fa96038b26 (patch) | |
| tree | 7ac021abc9b1e6f08dc64de6128868a28cabd175 /include/sata.h | |
| parent | f97db54d7e773a32100247ee002686b6a014a87d (diff) | |
| download | u-boot-1b5291dddf5f16c7ae10e3cb165882fa96038b26.tar.xz | |
85xx: Fix the clock adjust of mpc8569mds board
Currently the clk_adj is 6 (3/4 cycle), The settings will cause
the DDR controller hang at the data init. Change the clk_adj
from 6 to 4 (1/2 cycle), make the memory system stable.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Diffstat (limited to 'include/sata.h')
0 files changed, 0 insertions, 0 deletions