OMAP242x H4 board update

- fix for ES2 differences.
- switch to using the cfi_flash driver.
- fix SRAM build address.
- fix for GP device operation.
- unlock SRAM for GP devices.
- display more device information.
- fix potential deadlock in omap24xx_i2c driver.
- fix DLL load values to match dpllout*1 operation.
- fix 2nd chip select init for combo DDR device.
- add support for CFI Intel 28F256L18 on H4 board.
Patch by Richard Woodruff, 03 Mar 2005

8 files changed, 136 insertions, 189 deletions

diff --git a/include/asm-arm/arch-arm1136/clocks.h b/include/asm-arm/arch-arm1136/clocks.h
index bd1b088..2a95af1 100644
--- a/include/asm-arm/arch-arm1136/clocks.h
+++ b/include/asm-arm/arch-arm1136/clocks.h
@@ -57,8 +57,7 @@
 #define II_MPU_DIV       0x2    /* mpu = core/2 */
 #define II_DSP_DIV       0x343  /* dsp & iva divider */
 #define II_GFX_DIV       0x2
-#define II_BUS_DIV       0x04600C26
-#define II_BUS_DIV_ES1   0x04601026
+#define II_BUS_DIV       0x04601026
 #define II_DPLL_300      0x01832100
 
 /****************************************************************************;
@@ -87,8 +86,7 @@
 #define III_MPU_DIV       0x2    /* mpu = core/2 */
 #define III_DSP_DIV       0x23C3 /* dsp & iva divider sych enabled*/
 #define III_GFX_DIV       0x2
-#define III_BUS_DIV       0x08300c44
-#define III_BUS_DIV_ES1   0x08301044
+#define III_BUS_DIV       0x08301044
 #define III_DPLL_266      0x01885500
 
 /* set defaults for boot up */
@@ -98,7 +96,6 @@
 # define DSP_DIV          II_DSP_DIV
 # define GFX_DIV          II_GFX_DIV
 # define BUS_DIV          II_BUS_DIV
-# define BUS_DIV_ES1      II_BUS_DIV_ES1
 # define DPLL_VAL         II_DPLL_300
 #elif PRCM_CONFIG_III
 # define DPLL_OUT         III_DPLL_OUT_X2
@@ -106,7 +103,6 @@
 # define DSP_DIV          III_DSP_DIV
 # define GFX_DIV          III_GFX_DIV
 # define BUS_DIV          III_BUS_DIV
-# define BUS_DIV_ES1      III_BUS_DIV_ES1
 # define DPLL_VAL         III_DPLL_266
 #endif
 
diff --git a/include/asm-arm/arch-arm1136/i2c.h b/include/asm-arm/arch-arm1136/i2c.h
index 3e37f4d..7248950 100644
--- a/include/asm-arm/arch-arm1136/i2c.h
+++ b/include/asm-arm/arch-arm1136/i2c.h
@@ -33,6 +33,7 @@
 #define I2C_BUF                 (I2C_BASE + 0x14)
 #define I2C_CNT                 (I2C_BASE + 0x18)
 #define I2C_DATA                (I2C_BASE + 0x1c)
+#define I2C_SYSC                (I2C_BASE + 0x20)
 #define I2C_CON                 (I2C_BASE + 0x24)
 #define I2C_OA                  (I2C_BASE + 0x28)
 #define I2C_SA                  (I2C_BASE + 0x2c)
diff --git a/include/asm-arm/arch-arm1136/mem.h b/include/asm-arm/arch-arm1136/mem.h
index dfaf568..c81f1c4 100644
--- a/include/asm-arm/arch-arm1136/mem.h
+++ b/include/asm-arm/arch-arm1136/mem.h
@@ -13,7 +13,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -25,8 +25,8 @@
 #ifndef _OMAP24XX_MEM_H_
 #define _OMAP24XX_MEM_H_
 
-#define SDRC_CS0_OSET    0x0
-#define SDRC_CS1_OSET    0x30  /* mirror CS1 regs appear offset 0x30 from CS0 */
+#define SDRC_CS0_OSET	 0x0
+#define SDRC_CS1_OSET	 0x30  /* mirror CS1 regs appear offset 0x30 from CS0 */
 
 #ifndef __ASSEMBLY__
 /* struct's for holding data tables for current boards, they are getting used
@@ -40,8 +40,7 @@ struct sdrc_data_s {
 	u32    sdrc_rfr_ctrl;
 	u32    sdrc_mr_0_ddr;
 	u32    sdrc_mr_0_sdr;
-	u32    sdrc_dlla_ctrl;
-	u32    sdrc_dllb_ctrl;
+	u32    sdrc_dllab_ctrl;
 } /*__attribute__ ((packed))*/;
 typedef struct sdrc_data_s sdrc_data_t;
 
@@ -49,129 +48,109 @@ typedef enum {
 	STACKED		= 0,
 	IP_DDR		= 1,
 	COMBO_DDR	= 2,
-	IP_SDR	 	= 3,
+	IP_SDR		= 3,
 } mem_t;
 
 #endif
 
 /* Slower full frequency range default timings for x32 operation*/
-#define H4_2420_SDRC_SHARING               0x00000100
+#define H4_2420_SDRC_SHARING		0x00000100
 #define H4_2420_SDRC_MDCFG_0_SDR	0x00D04010 /* discrete sdr module */
 #define H4_2420_SDRC_MR_0_SDR		0x00000031
 #define H4_2420_SDRC_MDCFG_0_DDR	0x01702011 /* descrite ddr module */
 #define H4_2420_COMBO_MDCFG_0_DDR	0x00801011 /* combo module */
 #define H4_2420_SDRC_MR_0_DDR		0x00000032
 
-#ifndef CONFIG_OPTIMIZE_DDR
-# define H4_2420_SDRC_ACTIM_CTRLA_0	0x9bead909
-# define H4_2420_SDRC_ACTIM_CTRLB_0	0x00000014
-# define H4_2420_SDRC_RFR_CTRL_ES1	0x00002401
-# define H4_2420_SDRC_RFR_CTRL		0x0002da01
-#endif
-#define H4_2420_SDRC_DLLA_CTRL		0x0000E307 /* DLL value used for 50MHz */
-#define H4_2420_SDRC_DLLB_CTRL		0x0000E307 /* allow DPLLout*1 to work */
-
 #define H4_2422_SDRC_SHARING		0x00004b00
 #define H4_2422_SDRC_MDCFG_0_DDR	0x00801011 /* stacked ddr on 2422 */
-#ifndef CONFIG_OPTIMIZE_DDR
-# define H4_2422_SDRC_ACTIM_CTRLA_0	0x9BEAD909
-# define H4_2422_SDRC_ACTIM_CTRLB_0	0x00000020
-# define H4_2422_SDRC_RFR_CTRL_ES1	0x00002401
-# define H4_2422_SDRC_RFR_CTRL		0x0002da01
-#endif
 #define H4_2422_SDRC_MR_0_DDR		0x00000032
-#define H4_2422_SDRC_DLLA_CTRL		0x00007307
-#define H4_2422_SDRC_DLLB_CTRL		0x00007307
 
-/* optimized timings */
+/* ES1 work around timings */
+#define H4_242x_SDRC_ACTIM_CTRLA_0_ES1	0x9bead909  /* 165Mhz for use with 100/133 */
+#define H4_242x_SDRC_ACTIM_CTRLB_0_ES1	0x00000020
+#define H4_242x_SDRC_RFR_CTRL_ES1	    0x00002401	/* use over refresh for ES1 */
+
+/* optimized timings good for current shipping parts */
 #define H4_242X_SDRC_ACTIM_CTRLA_0_100MHz  0x5A59B485
 #define H4_242X_SDRC_ACTIM_CTRLB_0_100MHz  0x0000000e
-#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz  0x8BA6E6C8	/* temp warn 0 settigs */
-#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz  0x00000010   /* temp warn 0 settings */
-#define H4_242X_SDRC_RFR_CTRL_100MHz	0x0002da01	/* this is not optimal yet */
-#define H4_242X_SDRC_RFR_CTRL_133MHz	0x0003de01
-
-#ifdef CONFIG_OPTIMIZE_DDR
-# ifdef PRCM_CONFIG_II
-#  define H4_2420_SDRC_ACTIM_CTRLA_0	H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
-#  define H4_2420_SDRC_ACTIM_CTRLB_0	H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
-#  define H4_2420_SDRC_RFR_CTRL_ES1	H4_242X_SDRC_RFR_CTRL_100MHz
-#  define H4_2420_SDRC_RFR_CTRL		H4_242X_SDRC_RFR_CTRL_100MHz
-# elif PRCM_CONFIG_III
-#  define H4_2420_SDRC_ACTIM_CTRLA_0	H4_242X_SDRC_ACTIM_CTRLA_0_133MHz
-#  define H4_2420_SDRC_ACTIM_CTRLB_0	H4_242X_SDRC_ACTIM_CTRLB_0_133MHz
-#  define H4_2420_SDRC_RFR_CTRL_ES1	H4_242X_SDRC_RFR_CTRL_133MHz
-#  define H4_2420_SDRC_RFR_CTRL		H4_242X_SDRC_RFR_CTRL_133MHz
-# endif
-# define H4_2422_SDRC_ACTIM_CTRLA_0	H4_2420_SDRC_ACTIM_CTRLA_0
-# define H4_2422_SDRC_ACTIM_CTRLB_0	H4_2420_SDRC_ACTIM_CTRLB_0
-# define H4_2422_SDRC_RFR_CTRL_ES1	H4_2420_SDRC_RFR_CTRL_ES1
-# define H4_2422_SDRC_RFR_CTRL		H4_2420_SDRC_RFR_CTRL
+#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz  0x8BA6E6C8 /* temp warn 0 settings */
+#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz  0x00000010 /* temp warn 0 settings */
+#define H4_242X_SDRC_RFR_CTRL_100MHz	   0x0002da01
+#define H4_242X_SDRC_RFR_CTRL_133MHz	   0x0003de01
+#define H4_242x_SDRC_DLLAB_CTRL_100MHz	   0x0000980E /* 72deg, allow DPLLout*1 to work (combo)*/
+#define H4_242x_SDRC_DLLAB_CTRL_133MHz	   0x0000690E /* 72deg, for ES2 */
+
+#ifdef PRCM_CONFIG_II
+# define H4_2420_SDRC_ACTIM_CTRLA_0	H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
+# define H4_2420_SDRC_ACTIM_CTRLB_0	H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
+# define H4_2420_SDRC_RFR_CTRL		H4_242X_SDRC_RFR_CTRL_100MHz
+# define H4_2420_SDRC_DLLAB_CTRL    H4_242x_SDRC_DLLAB_CTRL_100MHz
+# define H4_2422_SDRC_ACTIM_CTRLA_0	H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
+# define H4_2422_SDRC_ACTIM_CTRLB_0	H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
+# define H4_2422_SDRC_RFR_CTRL		H4_242X_SDRC_RFR_CTRL_100MHz
+# define H4_2422_SDRC_DLLAB_CTRL    H4_242x_SDRC_DLLAB_CTRL_100MHz
+#elif PRCM_CONFIG_III
+# define H4_2420_SDRC_ACTIM_CTRLA_0	H4_242X_SDRC_ACTIM_CTRLA_0_133MHz
+# define H4_2420_SDRC_ACTIM_CTRLB_0	H4_242X_SDRC_ACTIM_CTRLB_0_133MHz
+# define H4_2420_SDRC_RFR_CTRL		H4_242X_SDRC_RFR_CTRL_133MHz
+# define H4_2420_SDRC_DLLAB_CTRL    H4_242x_SDRC_DLLAB_CTRL_133MHz
+# define H4_2422_SDRC_ACTIM_CTRLA_0	H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
+# define H4_2422_SDRC_ACTIM_CTRLB_0	H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
+# define H4_2422_SDRC_RFR_CTRL		H4_242X_SDRC_RFR_CTRL_100MHz
+# define H4_2422_SDRC_DLLAB_CTRL    H4_242x_SDRC_DLLAB_CTRL_100MHz
 #endif
 
 
 /* GPMC settings */
-#ifdef PRCM_CONFIG_II        /* L3 at 100MHz */
-#ifdef CFG_NAND_BOOT
-#define H4_24XX_GPMC_CONFIG1_0   0x0
-#define H4_24XX_GPMC_CONFIG2_0   0x00141400
-#define H4_24XX_GPMC_CONFIG3_0   0x00141400
-#define H4_24XX_GPMC_CONFIG4_0   0x0F010F01
-#define H4_24XX_GPMC_CONFIG5_0   0x010C1414
-#define H4_24XX_GPMC_CONFIG6_0   0x00000A80
-#else
-#define H4_24XX_GPMC_CONFIG1_0   0x3
-#define H4_24XX_GPMC_CONFIG2_0   0x000f0f01
-#define H4_24XX_GPMC_CONFIG3_0   0x00050502
-#define H4_24XX_GPMC_CONFIG4_0   0x0C060C06
-#define H4_24XX_GPMC_CONFIG5_0   0x01131F1F
-#endif
-#define H4_24XX_GPMC_CONFIG7_0   (0x00000C40|(H4_CS0_BASE >> 24))
-
-#define H4_24XX_GPMC_CONFIG1_1   0x00011000
-#define H4_24XX_GPMC_CONFIG2_1   0x001F1F00
-#define H4_24XX_GPMC_CONFIG3_1   0x00080802
-#define H4_24XX_GPMC_CONFIG4_1   0x1C091C09
-#define H4_24XX_GPMC_CONFIG5_1   0x031A1F1F
-#define H4_24XX_GPMC_CONFIG6_1   0x000003C2
-#define H4_24XX_GPMC_CONFIG7_1   (0x00000F40|(H4_CS1_BASE >> 24))
-#endif
-
-#ifdef PRCM_CONFIG_III  /* L3 at 133MHz */
-#ifdef CFG_NAND_BOOT
-#define H4_24XX_GPMC_CONFIG1_0   0x0
-#define H4_24XX_GPMC_CONFIG2_0   0x00141400
-#define H4_24XX_GPMC_CONFIG3_0   0x00141400
-#define H4_24XX_GPMC_CONFIG4_0   0x0F010F01
-#define H4_24XX_GPMC_CONFIG5_0   0x010C1414
-#define H4_24XX_GPMC_CONFIG6_0   0x00000A80
-#else
-#define H4_24XX_GPMC_CONFIG1_0   0x3
-#define H4_24XX_GPMC_CONFIG2_0   0x00151501
-#define H4_24XX_GPMC_CONFIG3_0   0x00060602
-#define H4_24XX_GPMC_CONFIG4_0   0x10081008
-#define H4_24XX_GPMC_CONFIG5_0   0x01131F1F
-#define H4_24XX_GPMC_CONFIG6_0   0x000004c4
-#endif
-#define H4_24XX_GPMC_CONFIG7_0   (0x00000C40|(H4_CS0_BASE >> 24))
-
-#define H4_24XX_GPMC_CONFIG1_1   0x00011000
-#define H4_24XX_GPMC_CONFIG2_1   0x001f1f01
-#define H4_24XX_GPMC_CONFIG3_1   0x00080803
-#define H4_24XX_GPMC_CONFIG4_1   0x1C091C09
-#define H4_24XX_GPMC_CONFIG5_1   0x041f1F1F
-#define H4_24XX_GPMC_CONFIG6_1   0x000004C4
-#define H4_24XX_GPMC_CONFIG7_1   (0x00000F40|(H4_CS1_BASE >> 24))
-#endif
-
-#ifdef CONFIG_APTIX /* SDRC-SDR for Aptix x16 */
-#define VAL_H4_SDRC_SHARING_16   0x00002400  /* No-Tristate, 16bit on D31-D16, CS1=dont care */
-#define VAL_H4_SDRC_SHARING      0x00000100
-#define VAL_H4_SDRC_MCFG_0_16    0x00901000  /* SDR-SDRAM,External,x16 bit */
-#define VAL_H4_SDRC_MCFG_0       0x01702011
-#define VAL_H4_SDRC_MR_0         0x00000029  /* Burst=2, Serial Mode, CAS 3*/
-#define VAL_H4_SDRC_RFR_CTRL_0   0x00001703  /* refresh time */
-#define VAL_H4_SDRC_DCDL2_CTRL   0x5A59B485
-#endif
-
-#endif
+#ifdef PRCM_CONFIG_II	     /* L3 at 100MHz */
+# ifdef CFG_NAND_BOOT
+#  define H4_24XX_GPMC_CONFIG1_0   0x0
+#  define H4_24XX_GPMC_CONFIG2_0   0x00141400
+#  define H4_24XX_GPMC_CONFIG3_0   0x00141400
+#  define H4_24XX_GPMC_CONFIG4_0   0x0F010F01
+#  define H4_24XX_GPMC_CONFIG5_0   0x010C1414
+#  define H4_24XX_GPMC_CONFIG6_0   0x00000A80
+# else	/* else NOR */
+#  define H4_24XX_GPMC_CONFIG1_0   0x3
+#  define H4_24XX_GPMC_CONFIG2_0   0x000f0f01
+#  define H4_24XX_GPMC_CONFIG3_0   0x00050502
+#  define H4_24XX_GPMC_CONFIG4_0   0x0C060C06
+#  define H4_24XX_GPMC_CONFIG5_0   0x01131F1F
+# endif /* endif CFG_NAND_BOOT */
+# define H4_24XX_GPMC_CONFIG7_0	  (0x00000C40|(H4_CS0_BASE >> 24))
+# define H4_24XX_GPMC_CONFIG1_1	  0x00011000
+# define H4_24XX_GPMC_CONFIG2_1	  0x001F1F00
+# define H4_24XX_GPMC_CONFIG3_1	  0x00080802
+# define H4_24XX_GPMC_CONFIG4_1	  0x1C091C09
+# define H4_24XX_GPMC_CONFIG5_1	  0x031A1F1F
+# define H4_24XX_GPMC_CONFIG6_1	  0x000003C2
+# define H4_24XX_GPMC_CONFIG7_1	  (0x00000F40|(H4_CS1_BASE >> 24))
+#endif /* endif PRCM_CONFIG_II */
+
+#ifdef PRCM_CONFIG_III	/* L3 at 133MHz */
+# ifdef CFG_NAND_BOOT
+#  define H4_24XX_GPMC_CONFIG1_0   0x0
+#  define H4_24XX_GPMC_CONFIG2_0   0x00141400
+#  define H4_24XX_GPMC_CONFIG3_0   0x00141400
+#  define H4_24XX_GPMC_CONFIG4_0   0x0F010F01
+#  define H4_24XX_GPMC_CONFIG5_0   0x010C1414
+#  define H4_24XX_GPMC_CONFIG6_0   0x00000A80
+# else	/* NOR boot */
+#  define H4_24XX_GPMC_CONFIG1_0   0x3
+#  define H4_24XX_GPMC_CONFIG2_0   0x00151501
+#  define H4_24XX_GPMC_CONFIG3_0   0x00060602
+#  define H4_24XX_GPMC_CONFIG4_0   0x10081008
+#  define H4_24XX_GPMC_CONFIG5_0   0x01131F1F
+#  define H4_24XX_GPMC_CONFIG6_0   0x000004c4
+# endif /* endif CFG_NAND_BOOT */
+# define H4_24XX_GPMC_CONFIG7_0	  (0x00000C40|(H4_CS0_BASE >> 24))
+# define H4_24XX_GPMC_CONFIG1_1	  0x00011000
+# define H4_24XX_GPMC_CONFIG2_1	  0x001f1f01
+# define H4_24XX_GPMC_CONFIG3_1	  0x00080803
+# define H4_24XX_GPMC_CONFIG4_1	  0x1C091C09
+# define H4_24XX_GPMC_CONFIG5_1	  0x041f1F1F
+# define H4_24XX_GPMC_CONFIG6_1	  0x000004C4
+# define H4_24XX_GPMC_CONFIG7_1	  (0x00000F40|(H4_CS1_BASE >> 24))
+#endif /* endif CFG_PRCM_III */
+
+#endif /* endif _OMAP24XX_MEM_H_ */
diff --git a/include/asm-arm/arch-arm1136/omap2420.h b/include/asm-arm/arch-arm1136/omap2420.h
index eba385c..7a7aae6 100644
--- a/include/asm-arm/arch-arm1136/omap2420.h
+++ b/include/asm-arm/arch-arm1136/omap2420.h
@@ -37,13 +37,25 @@
 #define A_WRITEPERM0          0x68005058
 #define GP_DEVICE             (BIT8|BIT9)
 
+/* L3 Firewall */
+#define A_REQINFOPERM0        0x68005048
+#define A_READPERM0           0x68005050
+#define A_WRITEPERM0          0x68005058
+
 /* CONTROL */
 #define OMAP2420_CTRL_BASE    (0x48000000)
 #define CONTROL_STATUS        (OMAP2420_CTRL_BASE + 0x2F8)
 
+/* device type */
+#define TST_DEVICE	0x0
+#define EMU_DEVICE	0x1
+#define HS_DEVICE	0x2
+#define GP_DEVICE	0x3
+
 /* TAP information */
 #define OMAP2420_TAP_BASE     (0x48014000)
 #define TAP_IDCODE_REG        (OMAP2420_TAP_BASE+0x204)
+#define PRODUCTION_ID         (OMAP2420_TAP_BASE+0x208)
 
 /* GPMC */
 #define OMAP2420_GPMC_BASE    (0x6800A000)
@@ -76,6 +88,7 @@
 #define OMAP2420_SDRC_BASE 0x68009000
 #define SDRC_SYSCONFIG     (OMAP2420_SDRC_BASE+0x10)
 #define SDRC_STATUS        (OMAP2420_SDRC_BASE+0x14)
+#define SDRC_CS_CFG        (OMAP2420_SDRC_BASE+0x40)
 #define SDRC_SHARING       (OMAP2420_SDRC_BASE+0x44)
 #define SDRC_DLLA_CTRL     (OMAP2420_SDRC_BASE+0x60)
 #define SDRC_DLLB_CTRL     (OMAP2420_SDRC_BASE+0x68)
diff --git a/include/asm-arm/arch-arm1136/rev.h b/include/asm-arm/arch-arm1136/rev.h
deleted file mode 100644
index 6fceb09..0000000
--- a/include/asm-arm/arch-arm1136/rev.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _OMAP24XX_REV_H_
-#define _OMAP24XX_REV_H_
-
-typedef	struct	h4_system_data {
-    /* base board info */
-    u32	   base_b_rev;         /* rev from base board i2c */
-    /* cpu board info */
-    u32	   cpu_b_rev;          /* rev from cpu board i2c */
-    u32    cpu_b_mux;          /* mux type on daughter board */
-    u32    cpu_b_ddr_type;     /* mem type */
-    u32    cpu_b_ddr_speed;    /* ddr speed rating */
-    u32    cpu_b_switches;     /* boot ctrl switch settings */
-    /* cpu info */
-    u32	   cpu_type;           /* type of cpu; 2420, 2422, 2430,...*/
-    u32    cpu_rev;            /* rev of given cpu; ES1, ES2,...*/
-} h4_sys_data;
-
-#define CDB_DDR_COMBO                   /* combo part on cpu daughter card */
-#define CDB_DDR_IPDB                    /* 2x16 parts on daughter card */
-
-#define DDR_100         100             /* type found on most mem d-boards */
-#define DDR_111         111             /* some combo parts */
-#define DDR_133         133             /* most combo, some mem d-boards */
-#define DDR_165         165             /* future parts */
-
-#define CPU_2420        0x2420
-#define CPU_2422        0x2422
-
-#define CPU_2422_ES1    1
-#define CPU_2422_ES2    2
-#define CPU_2420_ES1    1
-#define CPU_2420_ES2    2
-
-#endif
diff --git a/include/asm-arm/arch-arm1136/sys_info.h b/include/asm-arm/arch-arm1136/sys_info.h
index ef301ba..53c231a 100644
--- a/include/asm-arm/arch-arm1136/sys_info.h
+++ b/include/asm-arm/arch-arm1136/sys_info.h
@@ -39,7 +39,8 @@ typedef struct  h4_system_data {
 	u32 cpu_rev;		/* rev of given cpu; ES1, ES2,...*/
 } h4_sys_data;
 
-#define SDR_DISCRETE      4
+#define XDR_POP           5      /* package on package part */
+#define SDR_DISCRETE      4      /* 128M memory SDR module*/
 #define DDR_STACKED       3      /* stacked part on 2422 */
 #define DDR_COMBO         2      /* combo part on cpu daughter card (menalaeus) */
 #define DDR_DISCRETE      1      /* 2x16 parts on daughter card */
@@ -50,16 +51,19 @@ typedef struct  h4_system_data {
 #define DDR_165           165    /* future parts */
 
 #define CPU_2420          0x2420
-#define CPU_2422          0x2422
+#define CPU_2422          0x2422 /* 2420 + 64M stacked */
+#define CPU_2423          0x2423 /* 2420 + 96M stacked */
 
 #define CPU_2422_ES1      1
 #define CPU_2422_ES2      2
 #define CPU_2420_ES1      1
 #define CPU_2420_ES2      2
+#define CPU_2420_2422_ES1 1
 
 #define CPU_2420_CHIPID   0x0B5D9000
 #define CPU_24XX_ID_MASK  0x0FFFF000
 #define CPU_242X_REV_MASK 0xF0000000
+#define CPU_242X_PID_MASK 0x000F0000
 
 #define BOARD_H4_MENELAUS 1
 #define BOARD_H4_SDP      2
diff --git a/include/asm-arm/arch-arm1136/sys_proto.h b/include/asm-arm/arch-arm1136/sys_proto.h
index 2cd8455..9d8e5b2 100644
--- a/include/asm-arm/arch-arm1136/sys_proto.h
+++ b/include/asm-arm/arch-arm1136/sys_proto.h
@@ -44,10 +44,11 @@ u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound);
 u32 get_board_type(void);
 void display_board_info(u32);
 void update_mux(u32,u32);
+u32 get_sdr_cs_size(u32 offset);
 
 u32 running_in_sdram(void);
 u32 running_in_sram(void);
 u32 running_in_flash(void);
 u32 running_from_internal_boot(void);
-
+u32 get_device_type(void);
 #endif
diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h
index c791603..5674e20 100644
--- a/include/configs/omap2420h4.h
+++ b/include/configs/omap2420h4.h
@@ -39,11 +39,8 @@
 /*#define CONFIG_VIRTIO          1    #* Using Virtio simulator */
 
 /* Clock config to target*/
-#define PRCM_CONFIG_II		1
-/*#define PRCM_CONFIG_III	1 */
-
-/* Memory configuration on board */
-/*#define CONFIG_OPTIMIZE_DDR	1 */
+#define PRCM_CONFIG_II	1
+//#define PRCM_CONFIG_III		1
 
 #include <asm/arch/omap2420.h>        /* get chip and board defs */
 
@@ -125,11 +122,8 @@
 #ifdef CFG_NAND_BOOT
 #define CONFIG_COMMANDS          (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_NAND | CFG_CMD_JFFS2)
 #else
-#define CONFIG_COMMANDS          (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_JFFS2)
+#define CONFIG_COMMANDS          ((CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_JFFS2) & ~CFG_CMD_AUTOSCRIPT)
 #endif
-/* I'd like to get to these. Snap kernel loads if we make MMC go */
-  /* #define CONFIG_COMMANDS       (CONFIG_CMD_DFL | CFG_CMD_NAND | CFG_CMD_JFFS2 | CFG_CMD_DHCP | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_I2C) */
-
 #define CONFIG_BOOTP_MASK        CONFIG_BOOTP_DEFAULT
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@@ -241,17 +235,21 @@
 #define PHYS_SDRAM_1_SIZE        SZ_32M            /* at least 32 meg */
 #define PHYS_SDRAM_2             OMAP2420_SDRC_CS1
 
+#define PHYS_FLASH_SECT_SIZE     SZ_128K
 #define PHYS_FLASH_1             H4_CS0_BASE	   /* Flash Bank #1 */
 #define PHYS_FLASH_SIZE_1        SZ_32M
 #define PHYS_FLASH_2             (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */
 #define PHYS_FLASH_SIZE_2        SZ_32M
-#define CFG_FLASH_BASE           PHYS_FLASH_1
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
+#define CFG_FLASH_BASE           PHYS_FLASH_1
 #define CFG_MAX_FLASH_BANKS      2           /* max number of memory banks */
 #define CFG_MAX_FLASH_SECT       (259)	     /* max number of sectors on one chip */
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE /* Monitor at beginning of flash */
+#define CFG_MONITOR_LEN		SZ_128K      /* Reserve 1 sector */
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE, CFG_FLASH_BASE + PHYS_FLASH_SIZE_1 }
 
 #ifdef CFG_NAND_BOOT
 #define CFG_ENV_IS_IN_NAND	1
@@ -259,11 +257,24 @@
 #else
 #define CFG_ENV_ADDR             (CFG_FLASH_BASE + SZ_128K)
 #define	CFG_ENV_IS_IN_FLASH      1
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH_SECT_SIZE
+#define CFG_ENV_OFFSET	( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */
 #endif
 
+
+
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+#define CFG_FLASH_CFI		1	/* Flash memory is CFI compliant */
+#define CFG_FLASH_CFI_DRIVER	1	/* Use drivers/cfi_flash.c */
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* Use buffered writes (~10x faster) */
+#define CFG_FLASH_PROTECTION	1	/* Use hardware sector protection */
+
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT     (30*75*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT     (30*75*CFG_HZ) /* Timeout for Flash Write */
+#define CFG_FLASH_ERASE_TOUT     (100*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT     (100*CFG_HZ) /* Timeout for Flash Write */
 
 #define CFG_JFFS2_MEM_NAND