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authorVikas Manocha <vikas.manocha@st.com>2017-04-10 22:02:56 (GMT)
committerTom Rini <trini@konsulko.com>2017-05-08 15:39:05 (GMT)
commit6c9a10034a21680c4b2595d9b6468a767dedebca (patch)
treec39f998751f91fa06bf84d6096ac57b38e73d0e1 /include
parentd0b24c1aa96729d4d9fee02e2c60fc920068c6c5 (diff)
downloadu-boot-6c9a10034a21680c4b2595d9b6468a767dedebca.tar.xz
stm32f7: sdram: use sdram device tree node to configure sdram controller
Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
Diffstat (limited to 'include')
-rw-r--r--include/dt-bindings/memory/stm32-sdram.h34
1 files changed, 34 insertions, 0 deletions
diff --git a/include/dt-bindings/memory/stm32-sdram.h b/include/dt-bindings/memory/stm32-sdram.h
new file mode 100644
index 0000000..4cd6c2b
--- /dev/null
+++ b/include/dt-bindings/memory/stm32-sdram.h
@@ -0,0 +1,34 @@
+#ifndef DT_BINDINGS_STM32_SDRAM_H
+#define DT_BINDINGS_STM32_SDRAM_H
+
+#define NO_COL_8 0x0
+#define NO_COL_9 0x1
+#define NO_COL_10 0x2
+#define NO_COL_11 0x3
+
+#define NO_ROW_11 0x0
+#define NO_ROW_12 0x1
+#define NO_ROW_13 0x2
+
+#define MWIDTH_8 0x0
+#define MWIDTH_16 0x1
+#define MWIDTH_32 0x2
+#define BANKS_2 0x0
+#define BANKS_4 0x1
+#define CAS_1 0x1
+#define CAS_2 0x2
+#define CAS_3 0x3
+#define RD_BURST_EN 0x1
+#define RD_BURST_DIS 0x0
+#define RD_PIPE_DL_0 0x0
+#define RD_PIPE_DL_1 0x1
+#define RD_PIPE_DL_2 0x2
+
+#define TMRD_1 0x1
+#define TXSR_60 60
+#define TRAS_42 42
+#define TRC_60 60
+#define TRP_18 18
+#define TRCD_18 18
+
+#endif