diff options
author | Wolfgang Denk <wd@pollux.(none)> | 2005-08-02 12:43:57 (GMT) |
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committer | Wolfgang Denk <wd@pollux.(none)> | 2005-08-02 12:43:57 (GMT) |
commit | 7d939f89471d05ee40764156dd7147bca148c068 (patch) | |
tree | d486d08a91b344617454ee501678f184595d6ba3 /include | |
parent | 0f18cb6eef469688a1c57647e486c1341c045b9f (diff) | |
parent | 7770ce47e4904b295632cae95f24fa6f62eb9e32 (diff) | |
download | u-boot-7d939f89471d05ee40764156dd7147bca148c068.tar.xz |
Merge with /home/sr/git/u-boot
Diffstat (limited to 'include')
-rw-r--r-- | include/405gp_enet.h | 10 | ||||
-rw-r--r-- | include/440_i2c.h | 4 | ||||
-rw-r--r-- | include/440gx_enet.h | 8 | ||||
-rw-r--r-- | include/asm-ppc/processor.h | 2 | ||||
-rw-r--r-- | include/asm-ppc/u-boot.h | 7 | ||||
-rw-r--r-- | include/configs/bamboo.h | 316 | ||||
-rw-r--r-- | include/configs/bubinga.h (renamed from include/configs/BUBINGA405EP.h) | 169 | ||||
-rw-r--r-- | include/configs/ebony.h (renamed from include/configs/EBONY.h) | 125 | ||||
-rw-r--r-- | include/configs/ocotea.h (renamed from include/configs/OCOTEA.h) | 124 | ||||
-rw-r--r-- | include/configs/walnut.h (renamed from include/configs/WALNUT405.h) | 201 | ||||
-rw-r--r-- | include/configs/yellowstone.h | 298 | ||||
-rw-r--r-- | include/configs/yosemite.h | 312 | ||||
-rw-r--r-- | include/pci.h | 15 | ||||
-rw-r--r-- | include/ppc440.h | 219 | ||||
-rw-r--r-- | include/usb_defs.h | 14 |
15 files changed, 1590 insertions, 234 deletions
diff --git a/include/405gp_enet.h b/include/405gp_enet.h index 88ac4add..233ea11 100644 --- a/include/405gp_enet.h +++ b/include/405gp_enet.h @@ -67,7 +67,11 @@ struct arp_entry { /*Register addresses */ #if defined(CONFIG_440) +#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR) +#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00) +#else #define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780) +#endif #define ZMII_FER (ZMII_BASE) #define ZMII_SSR (ZMII_BASE + 4) #define ZMII_SMIISR (ZMII_BASE + 8) @@ -77,7 +81,11 @@ struct arp_entry { #endif /* CONFIG_440 */ #if defined(CONFIG_440) -#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800) +#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR) +#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00) +#else +#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800) +#endif #else #define EMAC_BASE 0xEF600800 #endif diff --git a/include/440_i2c.h b/include/440_i2c.h index b0ac592..01a5bac 100644 --- a/include/440_i2c.h +++ b/include/440_i2c.h @@ -1,7 +1,11 @@ #ifndef _440_i2c_h_ #define _440_i2c_h_ +#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR) +#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700) +#else #define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400) +#endif /*CONFIG_440_EP CONFIG_440_GR*/ #define I2C_REGISTERS_BASE_ADDRESS I2C_BASE_ADDR #define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF) diff --git a/include/440gx_enet.h b/include/440gx_enet.h index 8caf969..022c5d8 100644 --- a/include/440gx_enet.h +++ b/include/440gx_enet.h @@ -140,7 +140,11 @@ typedef struct emac_440gx_hw_st { /*ZMII Bridge Register addresses */ +#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR) +#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00) +#else #define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780) +#endif #define ZMII_FER (ZMII_BASE) #define ZMII_SSR (ZMII_BASE + 4) #define ZMII_SMIISR (ZMII_BASE + 8) @@ -272,7 +276,11 @@ typedef struct emac_440gx_hw_st { /* Ethernet MAC Regsiter Addresses */ +#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR) +#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00) +#else #define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800) +#endif #define EMAC_M0 (EMAC_BASE) #define EMAC_M1 (EMAC_BASE + 4) diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 71fadbc..806085e 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -716,6 +716,8 @@ #define PVR_405GPR_RB 0x50910951 #define PVR_440GP_RB 0x40120440 #define PVR_440GP_RC 0x40120481 +#define PVR_440EP_RA 0x42221850 +#define PVR_440EP_RB 0x422218D3 #define PVR_440GX_RA 0x51B21850 #define PVR_440GX_RB 0x51B21851 #define PVR_440GX_RC 0x51B21892 diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h index f8282d4..a759315 100644 --- a/include/asm-ppc/u-boot.h +++ b/include/asm-ppc/u-boot.h @@ -98,13 +98,18 @@ typedef struct bd_info { unsigned char bi_enet3addr[6]; #endif -#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440_GX) +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440_GX) || \ + defined(CONFIG_440_EP) || defined(CONFIG_440_GR) unsigned int bi_opbfreq; /* OPB clock in Hz */ int bi_iic_fast[2]; /* Use fast i2c mode */ #endif #if defined(CONFIG_NX823) unsigned char bi_sernum[8]; #endif +#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR) + int bi_phynum[2]; /* Determines phy mapping */ + int bi_phymode[2]; /* Determines phy mode */ +#endif #if defined(CONFIG_440_GX) int bi_phynum[4]; /* Determines phy mapping */ int bi_phymode[4]; /* Determines phy mode */ diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h new file mode 100644 index 0000000..da3c29f --- /dev/null +++ b/include/configs/bamboo.h @@ -0,0 +1,316 @@ +/* + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * bamboo.h - configuration for BAMBOO board + ***********************************************************************/ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_BAMBOO 1 /* Board is BAMBOO */ +#define CONFIG_440_EP 1 /* Specific PPC440EP support */ + +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#undef CFG_DRAM_TEST /* disable - takes long time! */ +//#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory */ +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 + + +/*Don't change either of these*/ +#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ +#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs */ +/*Don't change either of these*/ + +#define CFG_USB_DEVICE 0x50000000 +#define CFG_NVRAM_BASE_ADDR 0x80000000 +#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000) + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in SDRAM) + *----------------------------------------------------------------------*/ +#define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */ +#define CFG_INIT_RAM_END 0x2000 +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ +#define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */ +//#define CFG_SDRAM_BANKS (2) +#define CFG_SDRAM_BANKS (1) + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI 1 +/*define this if you want console on UART1*/ +#undef CONFIG_UART1_CONSOLE + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * NVRAM/RTC + * + * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF + * The DS1558 code assumes this condition + * + *----------------------------------------------------------------------*/ +#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */ +#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#if 0 /* test-only */ +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 256 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 120000 /* Timeout for Flash Write (in ms) */ +#else +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */ + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#endif + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/ +#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ +#define CFG_ENV_IS_IN_EEPROM 1 + +/* Define to allow the user to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CFG_I2C_MULTI_EEPROMS +#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */ +#define CFG_ENV_OFFSET 0x0 +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +#define CONFIG_BOOTCOMMAND "bootm 0xfe000000" /* autoboot command */ +#define CONFIG_BOOTDELAY 3 /* disable autoboot */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_NET_MULTI 1 /* required for netconsole */ +#define CONFIG_PHY1_ADDR 3 +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 10.0.4.251 +#define CONFIG_ETHADDR 00:10:EC:00:12:34 +#define CONFIG_ETH1ADDR 00:10:EC:00:12:35 + +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ +#define CONFIG_SERVERIP 10.0.4.115 + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +#ifdef CONFIG_440_EP +/* USB */ +#define CONFIG_USB_OHCI +#define CONFIG_USB_STORAGE + +/*Comment this out to enable USB 1.1 device*/ +#define USB_2_0_DEVICE +#endif /*CONFIG_440_EP*/ + +#ifdef DEBUG +#define CONFIG_PANIC_HANG +#else +#define CONFIG_HW_WATCHDOG /* watchdog */ +#endif + +#ifdef CONFIG_440_EP + /* Need to define POST */ +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ECHO | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + /* CFG_CMD_EXT2 |*/ \ + /* CFG_CMD_FAT |*/ \ + CFG_CMD_I2C | \ + /* CFG_CMD_IDE |*/ \ + CFG_CMD_IRQ | \ + /* CFG_CMD_KGDB |*/ \ + CFG_CMD_MII | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_FLASH | \ + /* CFG_CMD_SPI |*/ \ + CFG_CMD_USB | \ + 0 ) & ~CFG_CMD_IMLS) +#else +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ECHO | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + /* CFG_CMD_EXT2 |*/ \ + /* CFG_CMD_FAT |*/ \ + CFG_CMD_I2C | \ + /* CFG_CMD_IDE |*/ \ + CFG_CMD_IRQ | \ + /* CFG_CMD_KGDB |*/ \ + CFG_CMD_MII | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_FLASH | \ + /* CFG_CMD_SPI |*/ \ + 0 ) & ~CFG_CMD_IMLS) +#endif + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ +#define CONFIG_LYNXKDI 1 /* support kdi files */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT +#define CFG_PCI_MASTER_INIT + +#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ +#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/BUBINGA405EP.h b/include/configs/bubinga.h index 507cb75..c745195 100644 --- a/include/configs/BUBINGA405EP.h +++ b/include/configs/bubinga.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000, 2001 + * (C) Copyright 2000-2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -28,11 +28,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* Debug options */ -/*#define __DEBUG_START_FROM_SRAM__ */ -/*#define DEBUG 1*/ - - /* * High Level Configuration Options * (easy to change) @@ -40,7 +35,7 @@ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_BUBINGA405EP 1 /* ...on a BUBINGA405EP board */ +#define CONFIG_BUBINGA 1 /* ...on a BUBINGA board */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ @@ -49,8 +44,6 @@ #define CONFIG_NO_SERIAL_EEPROM /*#undef CONFIG_NO_SERIAL_EEPROM*/ /*----------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------*/ #ifdef CONFIG_NO_SERIAL_EEPROM /* @@ -75,49 +68,60 @@ #endif /*----------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------*/ - -/*#define CFG_ENV_IS_IN_FLASH 1*/ /* use FLASH for environment vars */ -#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ - -#ifdef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_FLASH -#else -#ifdef CFG_ENV_IS_IN_FLASH -#undef CFG_ENV_IS_IN_NVRAM -#endif -#endif - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ +/* + * Define here the location of the environment variables (FLASH or NVRAM). + * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only + * supported for backward compatibility. + */ #if 1 -#define CONFIG_BOOTCOMMAND "" /* autoboot command */ +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ #else -#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ +#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ #endif -/* Size (bytes) of interrupt driven serial port buffer. - * Set to 0 to use polling instead of interrupts. - * Setting to 0 will also disable RTS/CTS handshaking. - */ -#if 0 -#define CONFIG_SERIAL_SOFTWARE_FIFO 4000 -#else -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#endif +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=bubinga\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ + ":$(hostname):$(netdev):off panic=1\0" \ + "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm $(kernel_addr)\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm $(kernel_addr) $(ramdisk_addr)\0" \ + "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/bubinga/uImage\0" \ + "kernel_addr=fff80000\0" \ + "ramdisk_addr=fff90000\0" \ + "load=tftp 100000 /tftpboot/bubinga/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b 100000 fffc0000 40000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run net_nfs" #if 0 -#define CONFIG_BOOTARGS "root=/dev/nfs " \ - "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \ - "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4" +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ #else -#define CONFIG_BOOTARGS "root=/dev/hda1 " \ - "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0" - +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #endif +#define CONFIG_BAUDRATE 115200 + #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ @@ -126,29 +130,8 @@ #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */ -/* -#ifndef __DEBUG_START_FROM_SRAM__ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_KGDB | \ - CFG_CMD_DHCP | \ - CFG_CMD_DATE | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_ELF ) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_KGDB | \ - CFG_CMD_DHCP | \ - CFG_CMD_DATE | \ - CFG_CMD_DATE | \ - CFG_CMD_ELF ) -#endif -*/ - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ CFG_CMD_CACHE | \ CFG_CMD_DATE | \ CFG_CMD_DHCP | \ @@ -156,14 +139,13 @@ CFG_CMD_ELF | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ - CFG_CMD_KGDB | \ CFG_CMD_MII | \ CFG_CMD_NET | \ CFG_CMD_PCI | \ CFG_CMD_PING | \ CFG_CMD_REGINFO | \ CFG_CMD_SDRAM | \ - 0 ) + CFG_CMD_SNTP ) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -198,6 +180,7 @@ * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, * set Linux BASE_BAUD to 403200. */ +#undef CONFIG_SERIAL_SOFTWARE_FIFO #undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ #undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CFG_BASE_BAUD 691200 @@ -211,6 +194,17 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ + +/*----------------------------------------------------------------------- + * I2C stuff + *----------------------------------------------------------------------- + */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ @@ -224,7 +218,6 @@ #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ #endif - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- @@ -239,8 +232,8 @@ /* resource configuration */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ #define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */ #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ @@ -253,9 +246,6 @@ * External peripheral base address *----------------------------------------------------------------------- */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - #define CFG_KEY_REG_BASE_ADDR 0xF0100000 #define CFG_IR_REG_BASE_ADDR 0xF0200000 #define CFG_FPGA_REG_BASE_ADDR 0xF0300000 @@ -266,20 +256,11 @@ * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 -#ifdef __DEBUG_START_FROM_SRAM__ -#define CFG_SRAM_BASE 0xFFF80000 -#define CFG_FLASH_BASE 0xFFF00000 -#define CFG_MONITOR_BASE CFG_SRAM_BASE -#else #define CFG_SRAM_BASE 0xFFF00000 #define CFG_FLASH_BASE 0xFFF80000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#endif - - -/*#define CFG_MONITOR_LEN (200 * 1024) /XXX* Reserve 200 kB for Monitor */ -#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 200 kB for Monitor */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ +#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) /* * For booting Linux, the board info and command line data @@ -287,6 +268,7 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + /*----------------------------------------------------------------------- * FLASH organization */ @@ -296,13 +278,20 @@ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -/* BEG ENVIRONNEMENT FLASH */ +#define CFG_FLASH_ADDR0 0x5555 +#define CFG_FLASH_ADDR1 0x2aaa +#define CFG_FLASH_WORD_SIZE unsigned char + #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_OFFSET 0x00050000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ -#endif -/* END ENVIRONNEMENT FLASH */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif /* CFG_ENV_IS_IN_FLASH */ + /*----------------------------------------------------------------------- * NVRAM organization */ @@ -332,7 +321,6 @@ #define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ - /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in data cache) */ @@ -424,7 +412,6 @@ #define FPGA_REG1_OFFB_FLASH 0x02 /* Off board flash */ #define FPGA_REG1_SRAM_BOOT 0x01 /* SRAM at 0xFFF80000 not Flash */ - /* * Internal Definitions * diff --git a/include/configs/EBONY.h b/include/configs/ebony.h index 46e729f..ebd0b53 100644 --- a/include/configs/EBONY.h +++ b/include/configs/ebony.h @@ -36,20 +36,31 @@ #undef CFG_DRAM_TEST /* Disable-takes long time! */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ +/* + * Define here the location of the environment variables (FLASH or NVRAM). + * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only + * supported for backward compatibility. + */ +#if 1 +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#else +#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ +#endif + /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CFG_FLASH_BASE 0xff800000 /* start of FLASH */ -#define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */ +#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ #define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ #define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ #define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ -#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000) #define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) +#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000) /*----------------------------------------------------------------------- * Initial RAM & stack pointer (placed in internal SRAM) @@ -69,7 +80,7 @@ *----------------------------------------------------------------------*/ #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ -#define CONFIG_BAUDRATE 9600 +#define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400} @@ -87,16 +98,37 @@ #define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */ #define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ +#ifdef CFG_ENV_IS_IN_NVRAM +#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ +#define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) +#endif /* CFG_ENV_IS_IN_NVRAM */ + /*----------------------------------------------------------------------- * FLASH related *----------------------------------------------------------------------*/ #define CFG_MAX_FLASH_BANKS 3 /* number of banks */ #define CFG_MAX_FLASH_SECT 32 /* sectors per device */ -#undef CFG_FLASH_CHECKSUM #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#define CFG_FLASH_ADDR0 0x5555 +#define CFG_FLASH_ADDR1 0x2aaa +#define CFG_FLASH_WORD_SIZE unsigned char + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif /* CFG_ENV_IS_IN_FLASH */ + /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ @@ -112,22 +144,47 @@ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=ebony\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ + ":$(hostname):$(netdev):off panic=1\0" \ + "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm $(kernel_addr)\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm $(kernel_addr) $(ramdisk_addr)\0" \ + "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/ebony/uImage\0" \ + "kernel_addr=ff800000\0" \ + "ramdisk_addr=ff810000\0" \ + "load=tftp 100000 /tftpboot/ebony/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b 100000 fffc0000 40000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */ -#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ -#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ - -#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ -#define CFG_ENV_ADDR \ - (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) - -#define CONFIG_BOOTARGS "root=/dev/hda1 " -#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */ -#define CONFIG_BOOTDELAY -1 /* disable autoboot */ -#define CONFIG_BAUDRATE 9600 +#define CONFIG_BAUDRATE 115200 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ @@ -135,16 +192,22 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 8 /* PHY address */ - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_I2C | \ - CFG_CMD_KGDB | \ - CFG_CMD_DHCP | \ + CFG_CMD_ASKENV | \ CFG_CMD_DATE | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_ELF ) + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_SNTP ) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -173,6 +236,12 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ /*----------------------------------------------------------------------- * PCI stuff @@ -188,7 +257,7 @@ #define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ -#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ /* diff --git a/include/configs/OCOTEA.h b/include/configs/ocotea.h index 5e78b45..4f90b1b 100644 --- a/include/configs/OCOTEA.h +++ b/include/configs/ocotea.h @@ -1,6 +1,9 @@ /* * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com> * + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * * See file CREDITS for list of people who contributed to this * project. * @@ -85,6 +88,21 @@ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} /*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +/* + * Define here the location of the environment variables (FLASH or NVRAM). + * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only + * supported for backward compatibility. + */ +#if 1 +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#else +#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ +#endif + + +/*----------------------------------------------------------------------- * NVRAM/RTC * * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. @@ -97,6 +115,12 @@ #define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */ #define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ +#ifdef CFG_ENV_IS_IN_NVRAM +#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ +#define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) +#endif /* CFG_ENV_IS_IN_NVRAM */ + /*----------------------------------------------------------------------- * FLASH related *----------------------------------------------------------------------*/ @@ -107,6 +131,20 @@ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CFG_FLASH_ADDR0 0x5555 +#define CFG_FLASH_ADDR1 0x2aaa +#define CFG_FLASH_WORD_SIZE unsigned char + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif /* CFG_ENV_IS_IN_FLASH */ + /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ @@ -122,22 +160,46 @@ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=ocotea\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ + ":$(hostname):$(netdev):off panic=1\0" \ + "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm $(kernel_addr)\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm $(kernel_addr) $(ramdisk_addr)\0" \ + "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/ocotea/uImage\0" \ + "kernel_addr=fff00000\0" \ + "ramdisk_addr=fff10000\0" \ + "load=tftp 100000 /tftpboot/ocotea/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b 100000 fffc0000 40000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */ -#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ -#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ -#define CONFIG_ENV_OVERWRITE 1 - -#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ -#define CFG_ENV_ADDR \ - (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) - -#define CONFIG_BOOTARGS "root=/dev/hda1 " -#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */ -#define CONFIG_BOOTDELAY -1 /* disable autoboot */ #define CONFIG_BAUDRATE 115200 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ @@ -151,32 +213,22 @@ #define CONFIG_PHY3_ADDR 0x18 #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 10.1.2.3 -#define CONFIG_ETHADDR 00:04:AC:E3:28:8A -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:04:AC:E3:28:8B -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:04:AC:E3:28:8C -#define CONFIG_HAS_ETH3 -#define CONFIG_ETH3ADDR 00:04:AC:E3:28:8D -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ -#define CONFIG_SERVERIP 10.1.2.2 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_BEDBUG | \ + CFG_CMD_ASKENV | \ CFG_CMD_DATE | \ CFG_CMD_DHCP | \ CFG_CMD_DIAG | \ CFG_CMD_ELF | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ - CFG_CMD_KGDB | \ CFG_CMD_MII | \ CFG_CMD_NET | \ CFG_CMD_NFS | \ CFG_CMD_PCI | \ CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ CFG_CMD_SNTP ) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ @@ -206,22 +258,28 @@ #define CFG_HZ 100 /* decrementer freq: 1 ms ticks */ +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- */ /* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ /* Board-specific PCI */ #define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ -#define CFG_PCI_TARGET_INIT /* let board init pci target */ +#define CFG_PCI_TARGET_INIT /* let board init pci target */ -#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ /* @@ -233,7 +291,7 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 32768 /* For IBM 440 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/WALNUT405.h b/include/configs/walnut.h index 9155ce8..ac5b530 100644 --- a/include/configs/WALNUT405.h +++ b/include/configs/walnut.h @@ -1,6 +1,6 @@ /* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * (C) Copyright 2000-2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. * * See file CREDITS for list of people who contributed to this * project. @@ -35,51 +35,54 @@ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_WALNUT405 1 /* ...on a WALNUT405 board */ +#define CONFIG_WALNUT 1 /* ...on a WALNUT board */ + /* ...and on a SYCAMORE board */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ -/*#define CFG_ENV_IS_IN_FLASH 1*/ /* use FLASH for environment vars */ -#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=walnut\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ + ":$(hostname):$(netdev):off panic=1\0" \ + "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm $(kernel_addr)\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm $(kernel_addr) $(ramdisk_addr)\0" \ + "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/walnut/uImage\0" \ + "kernel_addr=fff80000\0" \ + "ramdisk_addr=fff80000\0" \ + "load=tftp 100000 /tftpboot/walnut/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b 100000 fffc0000 40000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run net_nfs" -#ifdef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_FLASH -#else -#ifdef CFG_ENV_IS_IN_FLASH -#undef CFG_ENV_IS_IN_NVRAM -#endif -#endif - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#if 1 -#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */ -#else -#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ -#endif - -/* Size (bytes) of interrupt driven serial port buffer. - * Set to 0 to use polling instead of interrupts. - * Setting to 0 will also disable RTS/CTS handshaking. - */ #if 0 -#define CONFIG_SERIAL_SOFTWARE_FIFO 4000 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ #else -#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #endif -#if 0 -#define CONFIG_BOOTARGS "root=/dev/nfs " \ - "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \ - "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4" -#else -#define CONFIG_BOOTARGS "root=/dev/hda1 " \ - "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0" - -#endif +#define CONFIG_BAUDRATE 115200 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ @@ -90,13 +93,21 @@ #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_KGDB | \ - CFG_CMD_DHCP | \ + CFG_CMD_ASKENV | \ CFG_CMD_DATE | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_ELF ) + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_SNTP ) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -131,6 +142,7 @@ * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, * set Linux BASE_BAUD to 403200. */ +#undef CONFIG_SERIAL_SOFTWARE_FIFO #undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ #undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CFG_BASE_BAUD 691200 @@ -144,12 +156,22 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ + +/*----------------------------------------------------------------------- + * I2C stuff + *----------------------------------------------------------------------- + */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- @@ -162,9 +184,10 @@ #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ @@ -173,26 +196,26 @@ #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ /*----------------------------------------------------------------------- - * External peripheral base address - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -#define CFG_KEY_REG_BASE_ADDR 0xF0100000 -#define CFG_IR_REG_BASE_ADDR 0xF0200000 -#define CFG_FPGA_REG_BASE_ADDR 0xF0300000 - -/*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0xFFF80000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ +#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) + +/* + * Define here the location of the environment variables (FLASH or NVRAM). + * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only + * supported for backward compatibility. + */ +#if 1 +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#else +#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ +#endif /* * For booting Linux, the board info and command line data @@ -200,22 +223,35 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + /*----------------------------------------------------------------------- * FLASH organization */ +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ + #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -/* BEG ENVIRONNEMENT FLASH */ +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#define CFG_FLASH_ADDR0 0x5555 +#define CFG_FLASH_ADDR1 0x2aaa +#define CFG_FLASH_WORD_SIZE unsigned char + #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_OFFSET 0x00050000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ -#endif -/* END ENVIRONNEMENT FLASH */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif /* CFG_ENV_IS_IN_FLASH */ + /*----------------------------------------------------------------------- * NVRAM organization */ @@ -227,30 +263,47 @@ #define CFG_ENV_ADDR \ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ #endif + /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup */ -#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ +/* Memory Bank 0 (Flash Bank 0) initialization */ +#define CFG_EBC_PB0AP 0x9B015480 +#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */ + +#define CFG_EBC_PB1AP 0x02815480 +#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ + +#define CFG_EBC_PB2AP 0x04815A80 +#define CFG_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ +#define CFG_EBC_PB3AP 0x01815280 +#define CFG_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ -/* Configuration Port location */ -#define CONFIG_PORT_ADDR 0xF0000500 +#define CFG_EBC_PB7AP 0x01815280 +#define CFG_EBC_PB7CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ + +/*----------------------------------------------------------------------- + * External peripheral base address + *----------------------------------------------------------------------- + */ +#define CFG_KEY_REG_BASE_ADDR 0xF0100000 +#define CFG_IR_REG_BASE_ADDR 0xF0200000 +#define CFG_FPGA_REG_BASE_ADDR 0xF0300000 /*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) + * Definitions for initial stack pointer and data area */ #define CFG_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */ diff --git a/include/configs/yellowstone.h b/include/configs/yellowstone.h new file mode 100644 index 0000000..90418e0 --- /dev/null +++ b/include/configs/yellowstone.h @@ -0,0 +1,298 @@ +/* + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * yellowstone.h - configuration for YELLOWSTONE board + ***********************************************************************/ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_YELLOWSTONE 1 /* Board is BAMBOO */ +#define CONFIG_440_GR 1 /* Specific PPC440GR support */ + +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#undef CFG_DRAM_TEST /* disable - takes long time! */ +#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xf0000000 /* start of FLASH */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory */ +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 + + +/*Don't change either of these*/ +#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ +#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs */ +/*Don't change either of these*/ + +#define CFG_USB_DEVICE 0x50000000 +#define CFG_NVRAM_BASE_ADDR 0x80000000 +#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000) + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in SDRAM) + *----------------------------------------------------------------------*/ +#define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */ +#define CFG_INIT_RAM_END 0x2000 +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ +#define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */ +#define CFG_SDRAM_BANKS (2) +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ +#define CONFIG_BAUDRATE 9600 +#define CONFIG_SERIAL_MULTI 1 +/*define this if you want console on UART1*/ +#undef CONFIG_UART1_CONSOLE + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * NVRAM/RTC + * + * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF + * The DS1558 code assumes this condition + * + *----------------------------------------------------------------------*/ +#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */ +#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 256 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 120000 /* Timeout for Flash Write (in ms) */ + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/ +#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ +#define CFG_ENV_IS_IN_EEPROM 1 + +/* Define to allow the user to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CFG_I2C_MULTI_EEPROMS +#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */ +#define CFG_ENV_OFFSET 0x0 +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +#define CONFIG_BOOTCOMMAND "bootm 0xfe000000" /* autoboot command */ +#define CONFIG_BOOTDELAY 3 /* disable autoboot */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_NET_MULTI 1 /* required for netconsole */ +#define CONFIG_PHY1_ADDR 3 +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 10.0.4.251 +#define CONFIG_ETHADDR 00:10:EC:00:12:34 +#define CONFIG_ETH1ADDR 00:10:EC:00:12:35 + +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ +#define CONFIG_SERVERIP 10.0.4.115 + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +#ifdef CONFIG_440_EP +/* USB */ +#define CONFIG_USB_OHCI +#define CONFIG_USB_STORAGE + +/*Comment this out to enable USB 1.1 device*/ +#define USB_2_0_DEVICE +#endif /*CONFIG_440_EP*/ + +#ifdef DEBUG +#define CONFIG_PANIC_HANG +#else +#define CONFIG_HW_WATCHDOG /* watchdog */ +#endif + +#ifdef CONFIG_440_EP + /* Need to define POST */ +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ECHO | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + /* CFG_CMD_EXT2 |*/ \ + /* CFG_CMD_FAT |*/ \ + CFG_CMD_I2C | \ + /* CFG_CMD_IDE |*/ \ + CFG_CMD_IRQ | \ + /* CFG_CMD_KGDB |*/ \ + CFG_CMD_MII | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_FLASH | \ + /* CFG_CMD_SPI |*/ \ + CFG_CMD_USB | \ + 0 ) & ~CFG_CMD_IMLS) +#else +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ECHO | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + /* CFG_CMD_EXT2 |*/ \ + /* CFG_CMD_FAT |*/ \ + CFG_CMD_I2C | \ + /* CFG_CMD_IDE |*/ \ + CFG_CMD_IRQ | \ + /* CFG_CMD_KGDB |*/ \ + CFG_CMD_MII | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_FLASH | \ + /* CFG_CMD_SPI |*/ \ + 0 ) & ~CFG_CMD_IMLS) +#endif + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ +#define CONFIG_LYNXKDI 1 /* support kdi files */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT +#define CFG_PCI_MASTER_INIT + +#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ +#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h new file mode 100644 index 0000000..5f88306 --- /dev/null +++ b/include/configs/yosemite.h @@ -0,0 +1,312 @@ +/* + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * yosemite.h - configuration for YOSEMITE board + ***********************************************************************/ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_YOSEMITE 1 /* Board is BAMBOO */ +#define CONFIG_440_EP 1 /* Specific PPC440EP support */ + +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#undef CFG_DRAM_TEST /* disable - takes long time! */ +#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory */ +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 + + +/*Don't change either of these*/ +#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ +#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs */ +/*Don't change either of these*/ + +#define CFG_USB_DEVICE 0x50000000 +#define CFG_NVRAM_BASE_ADDR 0x80000000 +#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000) + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in SDRAM) + *----------------------------------------------------------------------*/ +#define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */ +#define CFG_INIT_RAM_END 0x2000 +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ +#define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */ +#define CFG_SDRAM_BANKS (2) +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ +#define CONFIG_BAUDRATE 9600 +#define CONFIG_SERIAL_MULTI 1 +/*define this if you want console on UART1*/ +#undef CONFIG_UART1_CONSOLE + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * NVRAM/RTC + * + * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF + * The DS1558 code assumes this condition + * + *----------------------------------------------------------------------*/ +#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */ +#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#if 1 /* test-only */ +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 256 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 120000 /* Timeout for Flash Write (in ms) */ +#else +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */ + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#endif + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/ +#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ +#define CFG_ENV_IS_IN_EEPROM 1 + +/* Define to allow the user to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CFG_I2C_MULTI_EEPROMS +#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */ +#define CFG_ENV_OFFSET 0x0 +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +#define CONFIG_BOOTCOMMAND "bootm 0xfe000000" /* autoboot command */ +#define CONFIG_BOOTDELAY 3 /* disable autoboot */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_NET_MULTI 1 /* required for netconsole */ +#define CONFIG_PHY1_ADDR 3 +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 10.0.4.251 +#define CONFIG_ETHADDR 00:10:EC:00:12:34 +#define CONFIG_ETH1ADDR 00:10:EC:00:12:35 + +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ +#define CONFIG_SERVERIP 10.0.4.115 + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +#ifdef CONFIG_440_EP +/* USB */ +#define CONFIG_USB_OHCI +#define CONFIG_USB_STORAGE + +/*Comment this out to enable USB 1.1 device*/ +#define USB_2_0_DEVICE +#endif /*CONFIG_440_EP*/ + +#ifdef DEBUG +#define CONFIG_PANIC_HANG +#else +#define CONFIG_HW_WATCHDOG /* watchdog */ +#endif + +#ifdef CONFIG_440_EP + /* Need to define POST */ +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ECHO | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + /* CFG_CMD_EXT2 |*/ \ + /* CFG_CMD_FAT |*/ \ + CFG_CMD_I2C | \ + /* CFG_CMD_IDE |*/ \ + CFG_CMD_IRQ | \ + /* CFG_CMD_KGDB |*/ \ + CFG_CMD_MII | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_FLASH | \ + /* CFG_CMD_SPI |*/ \ + CFG_CMD_USB | \ + 0 ) & ~CFG_CMD_IMLS) +#else +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ECHO | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + /* CFG_CMD_EXT2 |*/ \ + /* CFG_CMD_FAT |*/ \ + CFG_CMD_I2C | \ + /* CFG_CMD_IDE |*/ \ + CFG_CMD_IRQ | \ + /* CFG_CMD_KGDB |*/ \ + CFG_CMD_MII | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_FLASH | \ + /* CFG_CMD_SPI |*/ \ + 0 ) & ~CFG_CMD_IMLS) +#endif + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ +#define CONFIG_LYNXKDI 1 /* support kdi files */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT +#define CFG_PCI_MASTER_INIT + +#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ +#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/pci.h b/include/pci.h index 458be23..8f19997 100644 --- a/include/pci.h +++ b/include/pci.h @@ -160,6 +160,21 @@ #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ +/* From 440ep */ +#define PCI_ERREN 0x48 /* Error Enable */ +#define PCI_ERRSTS 0x49 /* Error Status */ +#define PCI_BRDGOPT1 0x4A /* PCI Bridge Options 1 */ +#define PCI_PLBSESR0 0x4C /* PCI PLB Slave Error Syndrome 0 */ +#define PCI_PLBSESR1 0x50 /* PCI PLB Slave Error Syndrome 1 */ +#define PCI_PLBSEAR 0x54 /* PCI PLB Slave Error Address */ +#define PCI_CAPID 0x58 /* Capability Identifier */ +#define PCI_NEXTITEMPTR 0x59 /* Next Item Pointer */ +#define PCI_PMC 0x5A /* Power Management Capabilities */ +#define PCI_PMCSR 0x5C /* Power Management Control Status */ +#define PCI_PMCSRBSE 0x5E /* PMCSR PCI to PCI Bridge Support Extensions */ +#define PCI_BRDGOPT2 0x60 /* PCI Bridge Options 2 */ +#define PCI_PMSCRR 0x64 /* Power Management State Change Request Re. */ + /* Header type 2 (CardBus bridges) */ #define PCI_CB_CAPABILITY_LIST 0x14 /* 0x15 reserved */ diff --git a/include/ppc440.h b/include/ppc440.h index acd4572..3e9034f 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -78,7 +78,7 @@ #define ivor13 0x19d /* interrupt vector offset register 13 */ #define ivor14 0x19e /* interrupt vector offset register 14 */ #define ivor15 0x19f /* interrupt vector offset register 15 */ -#if defined(CONFIG_440_GX) +#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR) #define mcsrr0 0x23a /* machine check save/restore register 0 */ #define mcsrr1 0x23b /* mahcine check save/restore register 1 */ #define mcsr 0x23c /* machine check status register */ @@ -108,6 +108,7 @@ #define icdbtrh 0x39f /* instruction cache debug tag register high */ #define mmucr 0x3b2 /* mmu control register */ #define ccr0 0x3b3 /* core configuration register 0 */ +#define ccr1 0x378 /* core configuration for 440x5 only */ #define icdbdr 0x3d3 /* instruction cache debug data register */ #define dbdr 0x3f3 /* debug data register */ @@ -131,6 +132,7 @@ #define clk_opbd 0x00c0 #define clk_perd 0x00e0 #define clk_mald 0x0100 +#define clk_spcid 0x0120 #define clk_icfg 0x0140 /* 440gx sdr register definations */ @@ -149,19 +151,24 @@ #define sdr_ebc 0x0100 #define sdr_uart0 0x0120 /* UART0 Config */ #define sdr_uart1 0x0121 /* UART1 Config */ +#define sdr_uart2 0x0122 /* UART2 Config */ +#define sdr_uart3 0x0123 /* UART3 Config */ #define sdr_cp440 0x0180 #define sdr_xcr 0x01c0 #define sdr_xpllc 0x01c1 #define sdr_xplld 0x01c2 #define sdr_srst 0x0200 #define sdr_slpipe 0x0220 -#define sdr_amp 0x0240 +#define sdr_amp0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */ +#define sdr_amp1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */ #define sdr_mirq0 0x0260 #define sdr_mirq1 0x0261 #define sdr_maltbl 0x0280 #define sdr_malrbl 0x02a0 #define sdr_maltbs 0x02c0 #define sdr_malrbs 0x02e0 +#define sdr_pci0 0x0300 +#define sdr_usb0 0x0320 #define sdr_cust0 0x4000 #define sdr_sdstp2 0x4001 #define sdr_cust1 0x4002 @@ -234,6 +241,98 @@ #define xbcfg 0x23 /* external bus configuration reg */ #define xbcid 0x23 /* external bus core id reg */ +#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR) + +/* PLB4 to PLB3 Bridge OUT */ +#define P4P3_DCR_BASE 0x020 +#define p4p3_esr0_read (P4P3_DCR_BASE+0x0) +#define p4p3_esr0_write (P4P3_DCR_BASE+0x1) +#define p4p3_eadr (P4P3_DCR_BASE+0x2) +#define p4p3_euadr (P4P3_DCR_BASE+0x3) +#define p4p3_esr1_read (P4P3_DCR_BASE+0x4) +#define p4p3_esr1_write (P4P3_DCR_BASE+0x5) +#define p4p3_confg (P4P3_DCR_BASE+0x6) +#define p4p3_pic (P4P3_DCR_BASE+0x7) +#define p4p3_peir (P4P3_DCR_BASE+0x8) +#define p4p3_rev (P4P3_DCR_BASE+0xA) + +/* PLB3 to PLB4 Bridge IN */ +#define P3P4_DCR_BASE 0x030 +#define p3p4_esr0_read (P3P4_DCR_BASE+0x0) +#define p3p4_esr0_write (P3P4_DCR_BASE+0x1) +#define p3p4_eadr (P3P4_DCR_BASE+0x2) +#define p3p4_euadr (P3P4_DCR_BASE+0x3) +#define p3p4_esr1_read (P3P4_DCR_BASE+0x4) +#define p3p4_esr1_write (P3P4_DCR_BASE+0x5) +#define p3p4_confg (P3P4_DCR_BASE+0x6) +#define p3p4_pic (P3P4_DCR_BASE+0x7) +#define p3p4_peir (P3P4_DCR_BASE+0x8) +#define p3p4_rev (P3P4_DCR_BASE+0xA) + +/* PLB3 Arbiter */ +#define PLB3_DCR_BASE 0x070 +#define plb3_revid (PLB3_DCR_BASE+0x2) +#define plb3_besr (PLB3_DCR_BASE+0x3) +#define plb3_bear (PLB3_DCR_BASE+0x6) +#define plb3_acr (PLB3_DCR_BASE+0x7) + +/* PLB4 Arbiter - PowerPC440EP Pass1 */ +#define PLB4_DCR_BASE 0x080 +#define plb4_revid (PLB4_DCR_BASE+0x2) +#define plb4_acr (PLB4_DCR_BASE+0x3) +#define plb4_besr (PLB4_DCR_BASE+0x4) +#define plb4_bearl (PLB4_DCR_BASE+0x6) +#define plb4_bearh (PLB4_DCR_BASE+0x7) + +/* Nebula PLB4 Arbiter - PowerPC440EP */ +#define PLB_ARBITER_BASE 0x80 + +#define plb0_revid (PLB_ARBITER_BASE+ 0x00) +#define plb0_acr (PLB_ARBITER_BASE+ 0x01) +#define plb0_acr_ppm_mask 0xF0000000 +#define plb0_acr_ppm_fixed 0x00000000 +#define plb0_acr_ppm_fair 0xD0000000 +#define plb0_acr_hbu_mask 0x08000000 +#define plb0_acr_hbu_disabled 0x00000000 +#define plb0_acr_hbu_enabled 0x08000000 +#define plb0_acr_rdp_mask 0x06000000 +#define plb0_acr_rdp_disabled 0x00000000 +#define plb0_acr_rdp_2deep 0x02000000 +#define plb0_acr_rdp_3deep 0x04000000 +#define plb0_acr_rdp_4deep 0x06000000 +#define plb0_acr_wrp_mask 0x01000000 +#define plb0_acr_wrp_disabled 0x00000000 +#define plb0_acr_wrp_2deep 0x01000000 + +#define plb0_besrl (PLB_ARBITER_BASE+ 0x02) +#define plb0_besrh (PLB_ARBITER_BASE+ 0x03) +#define plb0_bearl (PLB_ARBITER_BASE+ 0x04) +#define plb0_bearh (PLB_ARBITER_BASE+ 0x05) +#define plb0_ccr (PLB_ARBITER_BASE+ 0x08) + +#define plb1_acr (PLB_ARBITER_BASE+ 0x09) +#define plb1_acr_ppm_mask 0xF0000000 +#define plb1_acr_ppm_fixed 0x00000000 +#define plb1_acr_ppm_fair 0xD0000000 +#define plb1_acr_hbu_mask 0x08000000 +#define plb1_acr_hbu_disabled 0x00000000 +#define plb1_acr_hbu_enabled 0x08000000 +#define plb1_acr_rdp_mask 0x06000000 +#define plb1_acr_rdp_disabled 0x00000000 +#define plb1_acr_rdp_2deep 0x02000000 +#define plb1_acr_rdp_3deep 0x04000000 +#define plb1_acr_rdp_4deep 0x06000000 +#define plb1_acr_wrp_mask 0x01000000 +#define plb1_acr_wrp_disabled 0x00000000 +#define plb1_acr_wrp_2deep 0x01000000 + +#define plb1_besrl (PLB_ARBITER_BASE+ 0x0A) +#define plb1_besrh (PLB_ARBITER_BASE+ 0x0B) +#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C) +#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D) + +#else + /*----------------------------------------------------------------------------- | Internal SRAM +----------------------------------------------------------------------------*/ @@ -265,6 +364,7 @@ #define l2_cache_snp1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */ #endif /* CONFIG_440_GX */ +#endif /* !CONFIG_440_EP !CONFIG_440_GR*/ /*----------------------------------------------------------------------------- | On-Chip Buses @@ -417,10 +517,8 @@ #define malrxbattr (MAL_DCR_BASE+0x15) /* RX descriptor base addr reg */ #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */ #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */ -#if defined(CONFIG_440_GX) #define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */ #define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg */ -#endif /* CONFIG_440_GX */ #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ #if defined(CONFIG_440_GX) @@ -893,6 +991,23 @@ #define SDR0_MFR_ECS_MASK 0x10000000 #define SDR0_MFR_ECS_INTERNAL 0x10000000 +#define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */ +#define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */ +#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ +#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ +#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ +#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */ +#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */ +#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ +#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ +#define SDR0_MFR_ERRATA3_EN0 0x00800000 +#define SDR0_MFR_ERRATA3_EN1 0x00400000 +#define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */ +#define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */ +#define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */ +#define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */ +#define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */ + #define SDR0_SRST_BGO 0x80000000 #define SDR0_SRST_PLB 0x40000000 #define SDR0_SRST_EBC 0x20000000 @@ -927,7 +1042,7 @@ /*-----------------------------------------------------------------------------+ | Clocking +-----------------------------------------------------------------------------*/ -#if !defined (CONFIG_440_GX) +#if !defined (CONFIG_440_GX) && !defined(CONFIG_440_EP) && !defined(CONFIG_440_GR) #define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */ #define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */ #define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */ @@ -945,7 +1060,7 @@ #define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */ #define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */ #define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */ -#else /* !CONFIG_440_GX */ +#else /* !CONFIG_440_GX or CONFIG_440_EP or CONFIG_440_GR */ #define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */ #define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */ #define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */ @@ -956,6 +1071,19 @@ #define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */ #define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */ +#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */ +#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ +#define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */ +#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */ +#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */ +#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ + +#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ +#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */ +#define PRADV_MASK 0x07000000 /* Primary Divisor A */ +#define PRBDV_MASK 0x07000000 /* Primary Divisor B */ +#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ + #define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */ #define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */ #define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */ @@ -1023,6 +1151,34 @@ #define PCIX0_CFGBASE (CFG_PCI_BASE + 0x0ec80000) #define PCIX0_IOBASE (CFG_PCI_BASE + 0x08000000) +#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR) + +/* PCI Local Configuration Registers + --------------------------------- */ +#define PCI_MMIO_LCR_BASE (CFG_PCI_BASE + 0x0f400000) /* Real => 0x0EF400000 */ + +/* PCI Master Local Configuration Registers */ +#define PCIX0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */ +#define PCIX0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */ +#define PCIX0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */ +#define PCIX0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */ +#define PCIX0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */ +#define PCIX0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */ +#define PCIX0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */ +#define PCIX0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */ +#define PCIX0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */ +#define PCIX0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */ +#define PCIX0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */ +#define PCIX0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */ + +/* PCI Target Local Configuration Registers */ +#define PCIX0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/Attribute */ +#define PCIX0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */ +#define PCIX0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/Attribute */ +#define PCIX0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */ + +#else + #define PCIX0_VENDID (PCIX0_CFGBASE + PCI_VENDOR_ID ) #define PCIX0_DEVID (PCIX0_CFGBASE + PCI_DEVICE_ID ) #define PCIX0_CMD (PCIX0_CFGBASE + PCI_COMMAND ) @@ -1079,6 +1235,52 @@ #define PCIX0_STS (PCIX0_CFGBASE + 0x00e0) +#endif /* !defined(CONFIG_440_EP) !defined(CONFIG_440_GR) */ + +/****************************************************************************** + * GPIO macro register defines + ******************************************************************************/ +#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR) +#define GPIO_BASE0 (CFG_PERIPHERAL_BASE+0x00000B00) +#define GPIO_BASE1 (CFG_PERIPHERAL_BASE+0x00000C00) + +#define GPIO0_OR (GPIO_BASE0+0x0) +#define GPIO0_TCR (GPIO_BASE0+0x4) +#define GPIO0_OSRL (GPIO_BASE0+0x8) +#define GPIO0_OSRH (GPIO_BASE0+0xC) +#define GPIO0_TSRL (GPIO_BASE0+0x10) +#define GPIO0_TSRH (GPIO_BASE0+0x14) +#define GPIO0_ODR (GPIO_BASE0+0x18) +#define GPIO0_IR (GPIO_BASE0+0x1C) +#define GPIO0_RR1 (GPIO_BASE0+0x20) +#define GPIO0_RR2 (GPIO_BASE0+0x24) +#define GPIO0_RR3 (GPIO_BASE0+0x28) +#define GPIO0_ISR1L (GPIO_BASE0+0x30) +#define GPIO0_ISR1H (GPIO_BASE0+0x34) +#define GPIO0_ISR2L (GPIO_BASE0+0x38) +#define GPIO0_ISR2H (GPIO_BASE0+0x3C) +#define GPIO0_ISR3L (GPIO_BASE0+0x40) +#define GPIO0_ISR3H (GPIO_BASE0+0x44) + +#define GPIO1_OR (GPIO_BASE1+0x0) +#define GPIO1_TCR (GPIO_BASE1+0x4) +#define GPIO1_OSRL (GPIO_BASE1+0x8) +#define GPIO1_OSRH (GPIO_BASE1+0xC) +#define GPIO1_TSRL (GPIO_BASE1+0x10) +#define GPIO1_TSRH (GPIO_BASE1+0x14) +#define GPIO1_ODR (GPIO_BASE1+0x18) +#define GPIO1_IR (GPIO_BASE1+0x1C) +#define GPIO1_RR1 (GPIO_BASE1+0x20) +#define GPIO1_RR2 (GPIO_BASE1+0x24) +#define GPIO1_RR3 (GPIO_BASE1+0x28) +#define GPIO1_ISR1L (GPIO_BASE1+0x30) +#define GPIO1_ISR1H (GPIO_BASE1+0x34) +#define GPIO1_ISR2L (GPIO_BASE1+0x38) +#define GPIO1_ISR2H (GPIO_BASE1+0x3C) +#define GPIO1_ISR3L (GPIO_BASE1+0x40) +#define GPIO1_ISR3H (GPIO_BASE1+0x44) +#endif + /* * Macros for accessing the indirect EBC registers */ @@ -1111,12 +1313,17 @@ typedef struct { unsigned long pllFwdDivB; unsigned long pllFbkDiv; unsigned long pllOpbDiv; + unsigned long pllPciDiv; unsigned long pllExtBusDiv; unsigned long freqVCOMhz; /* in MHz */ unsigned long freqProcessor; + unsigned long freqTmrClk; unsigned long freqPLB; unsigned long freqOPB; unsigned long freqEPB; + unsigned long freqPCI; + unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ + unsigned long pciClkSync; /* PCI clock is synchronous */ } PPC440_SYS_INFO; #endif /* _ASMLANGUAGE */ diff --git a/include/usb_defs.h b/include/usb_defs.h index 353019f..33d1e46 100644 --- a/include/usb_defs.h +++ b/include/usb_defs.h @@ -26,6 +26,20 @@ #ifndef _USB_DEFS_H_ #define _USB_DEFS_H_ + +/* Everything is aribtrary */ +#define USB_ALTSETTINGALLOC 4 +#define USB_MAXALTSETTING 128 /* Hard limit */ + +#define USB_MAX_DEVICE 32 +#define USB_MAXCONFIG 8 +#define USB_MAXINTERFACES 8 +#define USB_MAXENDPOINTS 16 +#define USB_MAXCHILDREN 8 /* This is arbitrary */ +#define USB_MAX_HUB 16 + +#define USB_CNTL_TIMEOUT 100 /* 100ms timeout */ + /* USB constants */ /* Device and/or Interface Class codes */ |