diff options
| author | Vikas Manocha <vikas.manocha@st.com> | 2017-04-10 22:03:03 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-05-08 15:57:22 (GMT) |
| commit | bfea69ad27936d619c0eb3c1be55cc292df8d7f5 (patch) | |
| tree | 14e38035d8f8d84ec50fc92a62536ced09a40e92 /include | |
| parent | a241c241cf2b08bb7905f4825e76e49944648b60 (diff) | |
| download | u-boot-bfea69ad27936d619c0eb3c1be55cc292df8d7f5.tar.xz | |
stm32f7: sdram: correct sdram configuration as per micron sdram
Actually the sdram memory on stm32f746 discovery board is micron part
MT48LC_4M32_B2B5_6A. This patch does the modification required in the
device tree node & driver for the same.
Also we are passing here all the timing parameters in terms of clock
cycles, so no need to convert time(ns or ms) to cycles.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/stm32f746-disco.h | 1 | ||||
| -rw-r--r-- | include/dt-bindings/memory/stm32-sdram.h | 15 |
2 files changed, 9 insertions, 7 deletions
diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index 73a316d..cc0f8fd 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -16,7 +16,6 @@ * Configuration of the external SDRAM memory */ #define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_RAM_FREQ_DIV 2 #define CONFIG_SYS_LOAD_ADDR 0xC0400000 #define CONFIG_LOADADDR 0xC0400000 diff --git a/include/dt-bindings/memory/stm32-sdram.h b/include/dt-bindings/memory/stm32-sdram.h index 4cd6c2b..89b719a 100644 --- a/include/dt-bindings/memory/stm32-sdram.h +++ b/include/dt-bindings/memory/stm32-sdram.h @@ -18,17 +18,20 @@ #define CAS_1 0x1 #define CAS_2 0x2 #define CAS_3 0x3 +#define SDCLK_2 0x2 #define RD_BURST_EN 0x1 #define RD_BURST_DIS 0x0 #define RD_PIPE_DL_0 0x0 #define RD_PIPE_DL_1 0x1 #define RD_PIPE_DL_2 0x2 -#define TMRD_1 0x1 -#define TXSR_60 60 -#define TRAS_42 42 -#define TRC_60 60 -#define TRP_18 18 -#define TRCD_18 18 +/* Timing = value +1 cycles */ +#define TMRD_2 (2 - 1) +#define TXSR_6 (6 - 1) +#define TRAS_4 (4 - 1) +#define TRC_6 (6 - 1) +#define TWR_2 (2 - 1) +#define TRP_2 (2 - 1) +#define TRCD_2 (2 - 1) #endif |